ADIS16201SLASHPCB datasheet(26/32 Pages) AD

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ADIS16201

Data Sheet

Rev. C | Page 26 of 32

Table 28. COMMAND Bit Descriptions

Bit

Description

15:8

Not used.

Software Reset Command. Allows for resetting of the

device via the SPI.

6:4

Not used.

Manual Flash Update Command. This command is

utilized in updating all of the nonvolatile registers to

flash. Once the command is initiated, the supply

voltage, VDD, must remain within specified limits for

50 ms to assure proper update of the nonvolatile

registers to flash.

Auxiliary DAC Latch Command. This command acts to

latch the AUX_DAC control register data into the

auxiliary DAC upon receipt of the command. This allows

for sequential loading of the upper and lower AUX_DAC

data bytes via the SPI without having the auxiliary DAC

transition into unwanted, intermediate states based

upon the individual AUX_DAC data bytes. Once the two

bytes of AUX_DAC are loaded, the DAC latch command

is initiated to move the data into the auxiliary DAC itself.

Factory Reset Command. Allows the user to reset all

four system level offset registers and all four system

level scale registers to the nominal settings (000h and

800h, respectively) upon receipt of command. Data

within the moving average filters will likewise be reset.

As the manual flash command identified below, this

command stores all of the nonvolatile registers to flash.

Once the command is initiated, the supply voltage, VDD,

must remain within specified limits for 50 ms to assure

proper update of the nonvolatile registers to flash.

Null Command. Loads the X/Y inclination offset as well

as the X/Y acceleration offset registers with values that

zero out the inclination and acceleration outputs.

Useful as a single command to simultaneously zero

both inclination and acceleration outputs. As the

manual flash command identified below, this command

stores all of the nonvolatile registers to flash. Once the

command is initiated, the supply voltage, VDD, must

remain within specified limits for 50 ms to assure

proper update of the nonvolatile registers to flash.

MISCELLANEOUS CONTROL REGISTER

The MSC_CTRL control register within the ADIS16201

provides control of two miscellaneous functions: the data-ready

hardware I/O function and the self-test function. The bits to

control these two functions are shown in Table 29.

The operation of the data-ready hardware I/O function is very

similar to the alarm hardware I/O function (controlled through

the ALM_CTRL control register). In this case, the MSC_CNTRL

serve as the hardware output pin that indicates when the

sampling, conversion, and processing of the seven data output

variables has been completed. This register provides the ability

to enable the data-ready hardware function and establish its

polarity.

The data-ready hardware I/O pin is reset automatically to an

inactive state part way through the next conversion cycle,

resulting in a pulse train with a duty cycle varying from ~15%

to 35%, depending upon the sample period setting. Upon

completion of the next sample/conversion/processing cycle, the

data ready hardware I/O line is reasserted.

The MSC_CTRL, ALM_CTRL, and GPIO_CTRL control

registers can influence the same GPIO pins. A priority level has

been established to avoid conflicting assignments of the two

GPIO pins. This priority level is defined as MSC_CTRL and has

precedence over ALM_CTRL, which has precedence over

GPIO_CTRL.

The self-test enable bit allows the user to place the ADIS16201

into a diagnostics mode for purposes of verifying the base

sensor’s operation. When this bit is set high, an electrostatic

force is generated internally to the sensor. The resulting

movement within the sensor allows the end user to test if the

accelerometer is functional. Typical change in the output is

328 mg (corresponding to 708 LSB). Once the self-test enable

bit is returned to a low state, normal operation is resumed.

MSC_CTRL Register Definition

Address

Default1

Format

Access

0x35, 0x34

0x0000

N/A

R/W

Default is valid only until the first register write cycle.

The 16-bit miscellaneous control register is used in the

controlling of the self-test and data-ready hardware functions.

This includes turning on and off the self-test function, as well as

enabling and configuring the data-ready function. For the data-

ready function, the written values are nonvolatile, allowing for

data recovery upon reset. The self-test data is volatile and is set

to 0s upon reset. This register has read/write capability.

Table 29. MSC_CTRL Bit Descriptions

Bit

Description

15:9

Not used.

Self-test enable.

1: ST enabled

0: ST disabled

7:3

Not used.

Data-ready enable.

1: DR enabled

0: DR disabled

Data-ready polarity.

1: Active high

0: Active low

Data-ready line select.

1: DIO1

0: DIO0

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