PowerPC 601 RISC Microprocessor Technical Summary

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3.2.1.8 User-Level SPRs

The following 601 SPRs are accessible by user-level software:

•

Link register (LR)—The link register can be used to provide the branch target address and to hold

the return address after branch and link instructions. The LR is 32 bits wide in 32-bit

implementations.

•

Count register (CTR)—The CTR is decremented and tested automatically as a result of branch-and-

count instructions. The CTR is 32 bits wide in 32-bit implementations.

•

Integer exception register (XER)—The 32-bit XER contains the integer carry and overflow bits and

two fields for the Load String and Compare Byte Indexed (lscbx) instruction (a POWER instruction

implemented in the 601 but not defined by the PowerPC architecture).

3.2.1.9 Supervisor-Level SPRs

The 601 also contains SPRs that can be accessed only by supervisor-level software. These registers consist

of the following:

•

The 32-bit data access exception (DAE)/source instruction service register (DSISR) defines the

cause of data access and alignment exceptions.

•

The data address register (DAR) is a 32-bit register that holds the address of an access after an

alignment or data access exception.

•

Decrementer register (DEC) is a 32-bit decrementing counter that provides a mechanism for

causing a decrementer exception after a programmable delay. PowerPC architecture defines that the

DEC frequency be provided as a subdivision of the processor clock frequency; however, the 601

implements a separate clock input that serves both the DEC and the RTC facilities.

•

The 32-bit table search description register 1(SDR1) specifies the page table format used in logical-

to-physical address translation for pages.

•

The machine status save/restore register 0 (SRR0) is a 32-bit register that is used by the 601 for

saving the address of the instruction that caused the exception, and the address to return to when a

Return from Interrupt (rfi) instruction is executed.

•

The machine status save/restore register 1 (SRR1) is a 32-bit register used to save machine status

on exceptions and to restore machine status when an rfi instruction is executed.

•

General SPRs, SPRG0–SPRG3, are 32-bit registers provided for operating system use.

•

The external access register (EAR) is a 32-bit register that controls access to the external control

facility through the External Control Input Word Indexed (eciwx) and External Control Output

Word Indexed (ecowx) instructions.

•

The processor version register (PVR) is a 32-bit, read-only register that identifies the version

(model) and revision level of the PowerPC processor.

•

Block address translation (BAT) registers—The PowerPC architecture defines 16 BAT registers,

divided into four pairs of data BATs (DBATs) and four pairs of instruction BATs (IBATs). The 601

includes four pairs of unified BATs (BAT0U–BAT3U and BAT0L–BAT3L). See Figure 3 for a list

of the SPR numbers for the BAT registers. Note that the format for the 601’s implementation of the

BAT registers differs from the PowerPC architecture definition.

Freescale Semiconductor, Inc.

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