PowerPC 601 RISC Microprocessor Technical Summary

21

The PowerPC architecture defines several of the exceptions differently than the 601 implementation. For

example, the PowerPC exception model provides a unique vector for the trace exception; the 601 vectors

trace exceptions to the run-mode exception handler. Other differences are noted in Section 3.5.2, “PowerPC

601 Microprocessor Exception Model.”

3.5.2 PowerPC 601 Microprocessor Exception Model

As specified by the PowerPC architecture, all 601 exceptions can be described as either precise or imprecise

and either synchronous or asynchronous. Asynchronous exceptions are caused by events external to the

processor’s execution; synchronous exceptions, which are all handled precisely by the 601, are caused by

instructions.

The 601 exception classes are shown in Table 1.

Although exceptions have other characteristics as well, such as whether they are maskable or nonmaskable,

the distinctions shown in Table 1 define categories of exceptions that the 601 handles uniquely. Note that

Table 1 includes no synchronous imprecise instructions. While the PowerPC architecture supports

imprecise handling of floating-point exceptions, the 601 implements these exception modes as precise

exceptions.

The 601’s exceptions, and conditions that cause them, are listed in Table 2. Exceptions that are specific to

the 601 are indicated.

Table 1. PowerPC 601 Microprocessor Exception Classifications

Synchronous/Asynchronous

Precise/Imprecise

Exception Type

Asynchronous

Imprecise

Machine check

System reset

Asynchronous

Precise

External interrupt

Decrementer

Synchronous

Precise

Instruction-caused exceptions

Table 2. Exceptions and Conditions

Exception

Type

Vector Offset

(hex)

Causing Conditions

Reserved

00000

—

System reset

00100

A system reset is caused by the assertion of either SRESET or HRESET.

Machine check

00200

A machine check is caused by the assertion of the TEA signal during a data bus

transaction.

Freescale Semiconductor, Inc.

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