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PowerPC 601 RISC Microprocessor Technical Summary

Part 1 PowerPC 601 Microprocessor Overview

Part 1 describes the features of the 601, provides a block diagram showing the major functional units, and

gives an overview of how the 601 operates.

The 601 is the first implementation of the PowerPC family of reduced instruction set computer (RISC)

microprocessors. The 601 implements the 32-bit portion of the PowerPC architecture, which provides 32-

bit effective (logical) addresses, integer data types of 8, 16, and 32 bits, and floating-point data types of 32

and 64 bits. For 64-bit PowerPC implementations, the PowerPC architecture provides 64-bit integer data

types, 64-bit addressing, and other features required to complete the 64-bit architecture.

The 601 is a superscalar processor capable of issuing and retiring three instructions per clock, one to each

of three execution units. Instructions can complete out of order for increased performance; however, the 601

makes execution appear sequential.

The 601 integrates three execution units—an integer unit (IU), a branch processing unit (BPU), and a

floating-point unit (FPU). The ability to execute three instructions in parallel and the use of simple

instructions with rapid execution times yield high efficiency and throughput for 601-based systems. Most

integer instructions execute in one clock cycle. The FPU is pipelined so a single-precision multiply-add

instruction can be issued every clock cycle.

The 601 includes an on-chip, 32-Kbyte, eight-way set-associative, physically addressed, unified instruction

and data cache and an on-chip memory management unit (MMU). The MMU contains a 256-entry, two-way

set-associative, unified translation lookaside buffer (UTLB) and provides support for demand paged virtual

memory address translation and variable-sized block translation. Both the UTLB and the cache use least

recently used (LRU) replacement algorithms.

The 601 has a 64-bit data bus and a 32-bit address bus. The 601 interface protocol allows multiple masters

to compete for system resources through a central external arbiter. Additionally, on-chip snooping logic

maintains cache coherency in multiprocessor applications. The 601 supports single-beat and burst data

transfers for memory accesses; it also supports both memory-mapped I/O and I/O controller interface

addressing.

The 601 uses an advanced, 3.6-V CMOS process technology and maintains full interface compatibility with

TTL devices.

1.1 PowerPC 601 Microprocessor Features

This section describes details of the 601’s implementation of the PowerPC architecture. Major features of

the 601 are as follows:

•

High-performance, superscalar microprocessor

— As many as three instructions in execution per clock (one to each of the three execution units)

— Single clock cycle execution for most instructions

— Pipelined FPU for all single-precision and most double-precision operations

•

Three independent execution units and two register files

— BPU featuring static branch prediction

— A 32-bit IU

— Fully IEEE 754-compliant FPU for both single- and double-precision operations

— Thirty-two GPRs for integer operands

— Thirty-two FPRs for single- or double-precision operands

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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