AD9389

Rev. 0 | Page 8 of 48

Pin Mnemonic

Description

POWER SUPPLY

Main Power Supply. These pins supply power to the main elements of the circuit. They should be filtered and as

quiet as possible.

Output Power Supply.

Clock Generator Power Supply. The most sensitive portion of the AD9389 is the clock generation circuitry. These

pins provide power to the clock PLL (phase-locked loop) and help the user design for optimal performance. The

designer should provide quiet, noise-free power to these pins.

GND

Ground. The ground return for all circuitry on-chip. It is recommended that the AD9389 be assembled on a single

solid ground plane, with careful attention given to ground current paths.

The SDA/SCL programming address can be 0x72 or 0x7A based on whether the PD/A0 pin is pulled high (10 kΩ resistor = 0x7A) or

pulled low (10 kΩ resistor = 0x72).

The EDID EEPROM on the receiver is expected to have an address of 0xA0.

LIST OF REFERENCE DOCUMENTS

Table 6.

Document

Description

EIA/CEA-861B

Describes audio and video infoframes as well as the E-EDID structure for HDMI.

HDMI v1.1

Defining document for HDMI Version 1.1. Can be located at www.hdmi.org.

HDCPv1.1

Defining document for HDCP Version 1.1. Can be located at www.digital-cp.com.

ITU-R BT.656-3

Defining document for BT656.

FORMAT STANDARDS

In this document, data is represented in a variety of ways.

Table 7.

Data Type

Format

0xNN

Hexadecimal (base-16) numbers are represented using the C language notation, preceded by 0x.

0bNN

Binary (base-2) numbers are represented using the C language notation, preceded by 0b.

NN

Decimal (base-10) numbers are represented using no additional prefixes or suffixes.

Bit

Bits are numbered in little-endian format, that is, the least significant bit (LSB) of a byte or word is referred to as Bit 0.