AD9389SLASHPCB datasheet(42/48 Pages) AD

42 / 48 page

AD9389

Rev. 0 | Page 42 of 48

PCB LAYOUT RECOMMENDATIONS

The AD9389 is a high precision, high speed analog device. As

such, to get the maximum performance out of the part, it is

important to have a well laid out board. The following is a guide

for designing a board using the AD9389.

POWER SUPPLY BYPASSING

It is recommended to bypass each power supply pin with a

0.1 μF capacitor. The exception is when two or more supply

pins are adjacent to each other. For these groupings of

powers/grounds, it is necessary to have only one bypass

capacitor. The fundamental idea is to have a bypass capacitor

within about 0.5 cm of each power pin. Also, avoid placing the

capacitor on the opposite side of the PC board from the

AD9389, as that interposes resistive vias in the path.

The bypass capacitors should be physically located between the

power plane and the power pin. Current should flow from the

power plane to the capacitor to the power pin. Do not make the

power connection between the capacitor and the power pin.

Placing a via underneath the capacitor pads, down to the power

plane, is generally the best approach.

It is particularly important to maintain low noise and good

stability of PVDD (the clock generator supply). Abrupt changes

in PVDD can result in similarly abrupt changes in sampling clock

phase and frequency. This can be avoided by careful attention to

regulation, filtering, and bypassing. It is highly desirable to

provide separate regulated supplies for each of the analog

circuitry groups (VDD and PVDD).

Some graphic controllers use substantially different levels of

power when active (during active picture time) and when idle

(during horizontal and vertical sync periods). This can result in

a measurable change in the voltage supplied to the analog

supply regulator, which can in turn produce changes in the

regulated analog supply voltage. This can be mitigated by

regulating the analog supply, or at least PVDD, from a different,

cleaner power source (for example, from a 12 V supply).

It is also recommended to use a single ground plane for the

entire board. Experience has shown repeatedly that the noise

performance is the same or better with a single ground plane.

Using multiple ground planes can be detrimental because each

separate ground plane is smaller, and long ground loops can

result.

In some cases, using separate ground planes is unavoidable,

therefore, it is recommended to place a single ground plane

under the AD9389. The location of the split should be at the

receiver of the digital outputs. For this case, it is even more

important to place components wisely because the current

loops are much longer (current takes the path of least

resistance).

DIGITAL INPUTS

The digital inputs on the AD9389 are designed to work with

1.8 V signals, but are tolerant of 3.3 V signals. Therefore, no

extra components need to be added if using 3.3 V logic.

Any noise that gets onto the HSYNC, VSYNC, or clock input

traces can add jitter to the system. Therefore, minimize the

trace lengths and do not run any digital or other high frequency

traces near them. All TMDS lines must maintain a 50 Ω

impedance trace and it is recommended that the trace lengths

be as short as possible. To request a sample layout, send email to

flatpanel_apps@analog.com.

AD9389/PCB датащи(PDF) 42 Page - Analog Devices

AD9389/PCB датащи(HTML) 42 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

датащи скачать

ссылки URL