AD7294 datasheet(24/45 Pages) AD

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AD7294

Preliminary Technical Data

Rev. PrB | Page 24 of 45

COMMAND REGISTER

Writing in this register puts the part into command mode.

While in command mode, the part cycles through the selected

channels on each subsequent read. If the external TSENSE channels

are selected in the command word, it is not actually requesting

a conversion, but the result of the last automatic conversion

will be output in sequence. See the Channel Sequence Register

section for information on autocycle mode.

Table 8. Address Pointer Byte—Command Bits

Parameter

Function

Convert on CH1

Convert on CH2

Convert on CH3

Convert on CH4

Convert on ISENSE1

Convert on ISENSE2

Read out last result from TSENSE1

Read out last result from TSENSE2

RESULT REGISTER

The result register is a 16-bit read/write register. The four

uncommitted input channels and the two ISENSE channels

converted results are stored in the result register for reading.

Writing to this register sets the DAC1 output code. The register

consists of bits D14 to D12 to identify the ADC channel

allocation. Bits D11 to D0, in the result register, are the data bits

sent to DAC1. While the MSB, D15, is reserved as an Alert_Flag

bit. The Alert_Flag bit indicates whether the conversion result

being read or any other channel result has violated the limit

registers associated with it. If an alert occurs, the master may

wish to read the alert status register to obtain more information

on where the alert occurred if the Alert_Flag bit is set.

Table 9 shows the contents of the first byte to read from the

AD7294; Table 10 shows the contents of the second byte read.

Table 9. Result Register (First Read)

MSB

LSB

D15

D14

D13

D12

D11

D10

Alert_Flag

CHID2

CHID1

CHID0

B11

B10

Table 10. Result Register (Second Read)

MSB

LSB

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