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AD7294

Preliminary Technical Data

Rev. PrB | Page 16 of 45

DAC OPERATION

The AD7294 contains four 12-bit DACs, which provide digital

control with 1.2 mV resolution to control the bias currents of

the power transistors. They can also be used to provide control

voltages for variable gain amplifiers or impedance match

networks in the main signal chain. The DAC core is a thin film

12-bit string DAC with a 5 V internal buffer to drive the high

voltage output stage. The DAC has a range of 0 to 5 V with a 2.5

V reference input. The output span of the DAC, which is

controlled by the offset input, can be positioned anywhere

between 0 to 15 V. Figure 16 is a block diagram of the DAC

architecture. The DAC can maintain 12-bit accuracy for up to a

500 Ω load.

VREF

12-Bit

DAC

100K

200K

100K

200K

VOUT

OFFSET IN

VDAC

I2CDATA INPUTS

EXTERNAL

REFERENCE

CAPACITOR

Figure 16. DAC Architecture

To improve functionality of the device, the DAC output is

digitally inverted. Therefore, although the input coding to the

DAC is straight binary, the ideal output voltage is given by

VDAC = VREF − VDAC*

Where VDAC *=

⎥⎦

⎤

⎢⎣

⎡

⎟

⎠

⎞

⎜

⎝

⎛

REF

where D is the decimal equivalent of the binary code that is loaded

to the DAC register, and n is the bit resolution of the DAC.

Table 5. DAC Output Code Table

Digital Input

Analog Output (V)

0000 0000 0000

VREF −VREF (0/4,096)=VREF

0000 0000 0001

VREF −VREF (1/4,096)

1000 0000 0000

VREF −VREF (2048/4,096) = VREF/2

1111 1111 1111

VREF −VREF (4095/4,096)

Resistor String

The resistor string structure is shown in Figure 17. It is simply a

string of 2n resistors, each of value R. The code loaded to the

DAC register determines at which node on the string the

voltage is tapped off to be fed into the output amplifier. The

voltage is tapped off by closing one of the switches connecting

the string to the amplifier. This architecture is inherently

monotonic, voltage out, and low glitch. It is also linear due to

the fact that all of the resistors are of equal value.

TO OUTPUT

AMPLIFIER

Figure 17. Resistor String Structure

Output Amplifier

Referring to Figure 16, the purpose of A1 is to buffer the DAC

output range from 0 V to VREF. The second amplifier, A2, is

configured such that when an offset is applied to OFFSET IN,

its output voltage is three times the offset voltage minus twice

the DAC voltage.

VOUT = 3VOFFSET − 2VDAC

The DAC word is digitally inverted on-chip such that

VOUT = 3VOFFSET + 2(VDAC* − VREF)

The user has the option of leaving the offset pin open, in which

case the voltage on the noninverting input of op amp, A2, is set

by the resistor divider, giving

VOUT = 2VDAC

This generates the 5 V output span from a 2.5 V reference.

Digitally inverting the DAC allows the circuit to operate as a

generic DAC when no offset is applied.

The DACs provide digital control with 1.2 mV resolution to

control the bias currents of the power transistors. The DAC

output buffer, A2, is capable of driving a 1 nF capacitor with

current source and sink capabilities of 10 mA to within 200 mV

off the supply. The output buffer has a supply range of 20 V with a

slew rate of 1 V/μs. Current limiting should take effect at about

40 mA. Note that a significant amount of power could be dissipated

in this situation; a thermal shutdown circuit will set the DAC

outputs to high impedance if a die temperature of >150°C is

measured by the internal temperature sensor.

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