AD7294 datasheet(12/45 Pages) AD

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AD7294

Preliminary Technical Data

Rev. PrB | Page 12 of 45

ADC INFORMATION

The AD7294 consists of a successive 200 kSPS approximation

analog-to-digital converter based around a capacitive DAC. The

analog input range for the part can be selected to be a 0 V to VREF

input or a 2 × VREF input, configured with either single-ended or

differential analog inputs. The AD7294 has an on-chip 2.5 V refer-

ence that can be n when an external reference is preferred. If the

internal reference is to be used elsewhere in a system, the output

must be buffered first.

The various monitored and uncommitted input signals are multi-

plexed into the ADC. The nine channel-allocation address bits

select which analog input channel to convert using the multiplexer.

Four uncommitted analog input channels are multiplexed to the

ADC, VIN (0 to 3). These four channels allow differential and

pseudodifferential mode measurements of various system signals.

ADC OPERATION

Figure 7 shows a very simplified schematic of the ADC. The

control logic, SAR and capacitive DACs are used to add and

subtract fixed amounts of charge from the sampling capacitor

arrays to bring the comparator back to a balanced condition.

CAPACITIVE

DAC

SWITCHES

VIN

VREF

SAR

CONTROL

LOGIC

CONTROL

INPUTS

OUTPUT DATA

14-BIT PARALLEL

COMPARATOR

Figure 7. Simplified ADC Block Diagram

Figure 8 and Figure 9 show simplified schematics of the ADC

during its acquisition and conversion phases in differential mode,

respectively. Figure 8 shows the ADC during its acquisition

phase. SW3 is closed, SW1 and SW2 are in Position A, the

comparator is held in a balanced condition, and the sampling

capacitor arrays acquire the differential signal on the input.

CAPACITIVE

DAC

CAPACITIVE

DAC

CONTROL

LOGIC

COMPARATOR

SW3

SW1

SW2

VIN+

VIN–

VREF

Figure 8. ADC Acquisition Phase

When the ADC starts a conversion, as shown in Figure 9, SW3

opens, and SW1 and SW2 move to Position B, causing the com-

parator to become unbalanced. Both inputs are disconnected

once the conversion begins. When the comparator is rebalanced,

the conversion is complete. The control logic generates the ADC

output code. The output impedances of the sources driving the

VIN+ and VIN− pins must be matched; otherwise, the two inputs

will have different settling times, resulting in errors.

CAPACITIVE

DAC

CAPACITIVE

DAC

CONTROL

LOGIC

COMPARATOR

SW3

SW1

SW2

VIN+

VIN–

VREF

Figure 9. ADC Conversion Phase

ADC TRANSFER FUNCTIONS

The designed code transitions occur at successive integer LSB

values (1 LSB, 2 LSB, and so on). In single-ended mode, the

LSB size is VREF/4,096 when the 0 V to VREF range is used and

2 × VREF/4,096 when the 0 V to 2 × VREF range is used.

000...000

111...111

1LSB = VREF/4096

1LSB

VREF – 1LSB

ANALOG INPUT

000...001

000...010

111...110

111...000

011...111

NOTE

1. VREF IS EITHER VREF OR 2 × VREF.

Figure 10. Straight Binary Transfer Characteristic

In differential mode, the LSB size is 2 × VREF /4,096 when the 0 V

to VREF range is used and 4 × VREF/4,096 when the 0 V to 2 × VREF

range is used. The ideal transfer characteristic for the ADC when

outputting straight binary coding is shown in Figure 10, and the

ideal transfer characteristic for the ADC when outputting twos

complement coding is shown in Figure 11 (this is shown with

the 2 × VREF range).

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