AD7294 datasheet(39/45 Pages) AD

39 / 45 page

Preliminary Technical Data

AD7294

Rev. PrB | Page 39 of 45

MODE 2 – AUTOCYCLE MODE

An automatic conversion cycle can be selected and enabled by

initially selecting the enable autocycle mode option in the

configuration register. The desired sequence of the autocycle

mode is controlled using the channel sequence register. The

automatic cycle mode can be set on the four uncommitted

analog input channels along with the two ISENSE channels. When

the 6 LSBs of this register are programmed with any

configuration other than all 0s, a conversion takes place every 5

ms. In autocycle mode the sample delay and bit trial delay are

two configuration options which can be used to maintain ADC

performance when I2C bus activity is taking place during a

conversion.

If more than one channel bit is set in the channel sequence

sequence, starting with the lowest channel. Once the sequence

is complete, the ADC starts converting on the lowest channel

again, continuing to loop through the sequence until the cycle

timer register contents are set to all 0s. This mode is useful for

monitoring signals, such as signal power and current sensing,

alerting only when the limits are violated. To exit the autocycle

mode the user must write all zeroes to the channel sequence

Figure 36 shows the autocycle mode where

only one channel is chosen from the channel sequence register.

Depending on the controller of the I2C interface, it is also

possible to break the long write frame into two shorter frames,

where a second frame can begin after writing to the

configuration register. After writing to the configuration

write to the channel sequence.

SD A

ACK. BY

AD7294

R/W

SC L

D15

D14

D13

D10

D11

FR AME 3

CONFIGURATION REGISTER VALUE MSB

SC L (CO NTINUED )

SD A (CONTINUED)

ST ART BY

MA ST ER

ACK. B Y

AD7294

ACK. BY

AD7294

FR AME 1

SERIAL BUS ADDRESS BYT E + WRITE

FRAME 2

POINTER TO CONFIGURATION REGISTER

ACK. BY

AD7294

FRAME 4

CONFIGURATION REGISTER VALUE LSB

ACK. BY

AD7294

ALERT CHID

D10

D11

FR AME 9

MOST SIGNIFICANT DATA BYTE

SC L (CO NTINUED )

SD A (CONTINUED)

NO ACK

AD7294

FRAME 10

LEAST SIGNIFICANT DATA BYTE

CHID

STOP BY

MASTER

ACK. BY

AD7294

FRA ME 5

POINTER TO CHANNEL SEQUENCE REGISTER

SC L (CONTINUED )

SD A (CO NTINUE D)

ACK. BY

AD7294

FRA ME 6

CHANNEL SEQUENCE REGISTER

SC L (CO NTINUED )

SD A (CONTINUED)

R/W

ACK. BY

AD7294

FRAME 8

SERIAL BUS ADDRESS BYTE + READ

REPEATED START

BY MASTER

FRAME 7

POINTER TO RESULT REGISTER

Figure 36. Autocycle Mode Operation

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