ADF4002 datasheet(18/24 Pages) AD

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ADF4002

Rev. 0 | Page 18 of 24

PFD

As the ADF4002 permits both R and N counters to be

programmed to 1, the part can effectively be used as a stand

alone PFD and charge pump. This is particularly useful in either

a clock cleaning application or a high performance LO. Addi-

tionally, the very low normalized phase noise floor (−222 dBc/Hz)

enables very low in-band phase noise levels. It is possible to

operate the PFD up to a maximum frequency of 200 MHz.

In Figure 22, the reference frequency equals the PFD, therefore,

R = 1. The charge pump output integrates into a stable control

voltage for the VCXO, and the output from the VCXO is

divided down to the desired PFD frequency using an external

divider.

REFIN

RSET

RFINA

RFINB

VDD

ADF4002

DECOUPLING CAPACITORS AND

INTERFACE SIGNALS HAVE BEEN

OMITTED FROM THE DIAGRAM IN

THE INTERESTS OF GREATER

CLARITY.

100pF

51Ω

10kΩ

LOOP

FILTER

GND

VCO

VCXO

VCC

GND

EXTERNAL PRESCALER

18Ω

100pF

RFOUT

VCC

Figure 22. ADF4002 as a PFD

INTERFACING

The ADF4002 has a simple SPI-compatible serial interface for

writing to the device. CLK, DATA, and LE control the data

transfer. When the latch enable (Pin LE) goes high, the 24 bits

that have been clocked into the input register on each rising

edge of CLK are transferred to the appropriate latch. For more

information, see Figure 2 for the timing diagram and Table 6 for

the latch truth table.

The maximum allowable serial clock rate is 20 MHz. This

means that the maximum update rate possible for the device is

833 kHz, or one update every 1.2 μs. This is certainly more than

adequate for systems that have typical lock times in hundreds of

microseconds.

ADuC812 Interface

Figure 23 shows the interface between the ADF4002 and the

ADuC812 MicroConverter®. Since the ADuC812 is based on an

8051 core, this interface can be used with any 8051-based

microcontroller. The MicroConverter is set up for SPI master

mode with CPHA = 0. To initiate the operation, the I/O port

driving LE is brought low. Each latch of the ADF4002 needs a

24-bit word. This is accomplished by writing three, 8-bit bytes

from the MicroConverter to the device. When the third byte

has been written, bring the LE input high to complete the

transfer.

On first applying power to the ADF4002, it needs four writes

(one each to the initialization latch, function latch, R counter

latch, and N counter latch) for the output to become active.

I/O port lines on the ADuC812 are also used to control power-

down (CE input) and to detect lock (MUXOUT configured as

lock detect and polled by the port input).

When operating in the SPI master mode, the maximum

SCLOCK rate of the ADuC812 is 4 MHz. This means that the

maximum rate at which the output frequency can be changed is

166 kHz.

CLK

DATA

MUXOUT

(LOCK DETECT)

MOSI

SCLOCK

I/O PORTS

ADuC812

ADF4002

Figure 23. ADuC812 to ADF4002 Interface

ADSP2181 Interface

Figure 24 shows the interface between the ADF4002 and the

ADSP21xx digital signal processor. The ADF4002 needs a

24-bit serial word for each latch write. The easiest way to

accomplish this using the ADSP21xx family is to use the

autobuffered transmit mode of operation with alternate

framing. This provides a means for transmitting an entire block

of serial data before an interrupt is generated. Set up the word

length for 8 bits and use three memory locations for each 24-bit

word. To program each 24-bit latch, store the three 8-bit bytes,

enable the autobuffered mode, and then write to the transmit

transfer.

CLK

DATA

MUXOUT

(LOCK DETECT)

ADSP21xx

ADF4002

SCLK

I/O FLAGS

TFS

Figure 24. ADSP-21xx to ADF4002 Interface

PCB DESIGN GUIDELINES FOR CHIP SCALE

PACKAGE

The lands on the lead frame chip scale package (CP-20-1) are

rectangular. The printed circuit board pad for these should be

0.1 mm longer than the package land length and 0.05 mm wider

than the package land width. The land should be centered on

the pad. This ensures that the solder joint size is maximized.

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