ADF4002 datasheet(9/24 Pages) AD

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ADF4002

Rev. 0 | Page 9 of 24

CLR1

CLR2

DOWN

ABP2

ABP1

CPGND

R DIVIDER

PROGRAMMABLE

DELAY

N DIVIDER

CHARGE

PUMP

Figure 14. PFD Simplified Schematic and Timing (In Lock)

MUXOUT AND LOCK DETECT

The output multiplexer on the ADF4002 allows the user to

access various internal points on the chip. The state of

MUXOUT is controlled by M3, M2, and M1 in the function

latch. Figure 19 shows the full truth table. Figure 15 shows the

MUXOUT section in block diagram form.

DGND

DVDD

CONTROL

MUX

ANALOG LOCK DETECT

DIGITAL LOCK DETECT

R COUNTER OUTPUT

N COUNTER OUTPUT

SDOUT

MUXOUT

Figure 15. MUXOUT Circuit

Lock Detect

MUXOUT can be programmed for two types of lock detect:

digital lock detect and analog lock detect.

Digital lock detect is active high. When LDP in the R counter

latch is set to 0, digital lock detect is set high when the phase

error on three consecutive phase detector (PD) cycles is less

than 15 ns. With LDP set to 1, five consecutive cycles of less

than 15 ns are required to set the lock detect. It stays set at high

until a phase error of greater than 25 ns is detected on any

subsequent PD cycle. For PFD frequencies greater than 10 MHz,

analog lock detect is more accurate because of the smaller pulse

widths.

The N-channel, open-drain, analog lock detect should be

operated with an external pull-up resistor of 10 kΩ nominal.

When lock has been detected this output is high with narrow,

low-going pulses.

INPUT SHIFT REGISTER

The ADF4002 digital section includes a 24-bit input shift

clocked into the 24-bit shift register on each rising edge of CLK.

The data is clocked in MSB-first. Data is transferred from the

shift register to one of four latches on the rising edge of LE. The

destination latch is determined by the state of the two control

bits (C2, C1) in the shift register. These are the two LSBs, DB1

and DB0, as shown in the timing diagram (see Figure 2). Table 6

provides the truth table for these bits. Figure 16 shows a

summary of how the latches are programmed.

Table 6. C2, C1 Truth Table

Control Bits

Data Latch

R Counter

N Counter

Function Latch

Initialization Latch

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