SN250 datasheet(112/130 Pages) STMICROELECTRONICS

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Functional description—application modules

SN250

112/130

All interrupt source signals (except level-triggered GPIO interrupt signals) are momentary

pulses that are guaranteed to be a single cycle of the main 12MHz clock. They will

synchronously set the corresponding interrupt source bit(s) within a set of hierarchically

organized interrupt source register(s). The interrupt controller merges these hierarchical

interrupt sources into the single interrupt input to the CPU. Table 37 illustrates the enable

and configuration status of each event within the SN250.

The hierarchy has two levels of interrupt source and associated mask registers for fine

control of interrupt processing. The top-level INT_FLAG and INT_CFG registers have one

bit per major functional module of the SN250. The second level is a set of

INT_periphFLAG

and INT_periphCFG registers that each have one bit per sub-function

within their respective module. Some modules, like ADC, have no second level. For a top-

level event to actually interrupt the CPU, it must be enabled in the top-level INT_CFG

INT_periphCFG

registers.

To clear (acknowledge) an interrupt, software must write a 1 into the corresponding bit of the

interrupt’s lowest level INT_periphFLAG register. For example, to acknowledge an ADC

interrupt, which has no second level, software must write a 1 into the INT_ADC bit of the top-

level INT_FLAG register. To acknowledge a SC1 RXVALID second-level interrupt, software

must write a 1 into the INT_SCRXVAL bit of the second-level INT_SC1FLAG register. If there

were other enabled SC1 interrupts pending, the top-level INT_SC1 bit in the INT_FLAG

events. The interrupt source register bits are designed to remain set if the event reoccurs at

the same moment the bit is being cleared to acknowledge a prior occurrence.

If another enabled interrupt of the same type occurs before being acknowledged by the

software ISR, it will be lost because no counting or queuing is used. However, this condition

is detected and stored in the top-level INT_MISS register to facilitate software detection of

such problems. The INT_MISS register is “acknowledged” in the same way as the

INT_FLAG

If another enabled interrupt occurs after being acknowledged but while interrupts remain

disabled, the CPU will be re-interrupted to service it when the software ISR returns and

interrupts are re-enabled.

Applications only have write access to certain bits in the top-level INT_FLAG, INT_CFG,

and INT_MISS registers that pertain to application peripherals. They have full access to

second-level INT_periphFLAG and INT_periphCFG registers for application peripherals.

System peripheral events and masking are protected from application interference.

Applications can also trigger a software interrupt by writing into the INT_SWCTRL register.

System software is responsible for processing and acknowledging this interrupt.

The SN250 also provides a global INT_EN enable bit to enable or disable all interrupts into

the CPU. This bit can be used to easily protect brief critical sections in application or system

software.

Table 37.

Event enable and configuration status

Event

Configuration

Interrupt pin to CPU

INT_EN

Top: INT_FLAG

INT_CFG

2nd: INT_periphFLAG

INT_periphCFG

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