SN250 datasheet(109/130 Pages) STMICROELECTRONICS

109 / 130 page

SN250

Functional description—application modules

109/130

To ensure the pipelined digital filter in the ADC is flushed, ADC_EN should be cleared before

changes are made to ADC_SEL or ADC_RATE. Discard the first sample after ADC_EN is set.

The ADC uses an internal reference, VREF, which may be routed out to the alternate pin

function of GPIO8, VREF_OUT. VREF_OUT is only enabled when the ADC_EN bit in the

ADC_CFG

software, using the regulated supply (VDD) as reference. VREF is able to source modest

current (see Table 36) and is stable under capacitive loads. The ADC cannot accept an

external VREF input. For selecting alternate pin functions, refer to Table 17 and Table 18.

While the ADC Module supports both single-ended and differential inputs, the ADC input

stage is differential. Single-ended operation is provided by internally connecting one of the

differential inputs to VREF/2 while fully differential operation uses two external signals. The

full-scale differential input range spans -VREF to +VREF and the single-ended input range

spans 0 to VREF.

Fully differential operation is recommended only when large common-mode signals are

present. To correct differential input for offset and gain, each side of the input should be

sampled individually using single-ended operation, so that they may be calibrated against

VREF.

Sampling of internal connections VSS and VREF allow for offset and gain calibration of the

ADC in applications where absolute accuracy is important. Measurement of the unregulated

supply VDD_PADS, 2.1-3.6V pad supply, allows battery voltage to be monitored.

Measurement of the regulated supply VDD, 1.8V core supply, provides an accurate means

of calibrating the ADC as the regulator is factory trimmed.

Offset and gain correction using VREF or VDD reduces both ADC gain errors and reference

errors but it is limited by the absolute accuracy of the supply. Correction using VREF is

recommended because VREF is calibrated by the ZNet software against VDD, which is

factory trimmed. Table 35 shows the equations used.

Table 35.

Offset and gain correction calculation

Calculation Type

Corrected Sample

Absolute Voltage

Offset corrected

Offset and gain corrected using VREF,

normalized to VREF

Offset and gain corrected using VDD,

normalized to VDD

VSS

–

()

VSS

–

() 16

VREF

VSS

–

()

---------------------------------------------

NVREF

()

--------------------------------

VSS

–

() 16

VDD

VSS

–

()

--------------------------------------------------

NVDD

()

----------------------------

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