5

Integration guidance

5.1

Typical hardware implementation

The Physical Presence (PP) pin should be connected if platform implementation (at boot level) uses a hardware

physical presence function.

The figure below shows the hardware implementation for the VFQFPN32 package.

Figure 11. Typical hardware implementation (VFQFPN32 package)

7

6

1

VPS

100 nF

10 µF

GND

SPI_MISO

SPI_MOSI

SPI_CS

SPI_CLK

SPI_PIRQ

SPI_RST

GPIO_PP (opt)

GPIO_LP (opt)

33 Ω

33 Ω

33 Ω

Surrounds optional

components

VFQFPN32

NiC

2 GND

3 NiC

4 NiC

5 NiC

GPIO_LP

GPIO_PP

8 NiC

SPI_MISO

NiC

VPS

SPIMOSI

SPI_CS

SPI_CLK

SPI_PIRQ

SPI_RST

24

23

22

21

20

19

18

17

33

NiC

56 µF

Note:

The use of a low-value resistor (typically 33 Ω) on SPI_MISO, SPI_MOSI and SPI_CLK can be recommended

for line adaptation when the signals are affected by parasite spikes. It can also be recommended to avoid

disturbance of the ramp-up and ramp-down signals.

The capacitor on SPI_CS is optional. Its use is recommended when the SPI_CLK signal is high in SPI mode 0

(see Section 3.6 Integration requirements).

ST33TPHF2XSPI

Integration guidance

DS14186 - Rev 1

page 17/35