Figure 8. SPI slave timing diagram - SPI_CLK high (by default)

CPHA=0

SPI_MOSI

input

SPI_MISO

output

MSB OUT

MSB IN

BIT6 OUT

LSB IN

LSB OUT

CPOL=0

BIT1 IN

SPI_NSS input

tSU(NSS)

tc(SCK)

th(NSS)

ta(SO)

tw(SCKH)

tv(SO)

th(SO)

tdis(SO)

tsu(SI)

th(SI)

tdelay

Note:

1.

For both drawings, measurements are made at CMOS levels: 0.3 × VPS and 0.7 × VPS.

2.

When no communication is ongoing the data output line of the SPI (SPI_MOSI in Master mode,

SPI_MISO in Slave mode) has its alternate function capability released. In this case, the pin status

depends on the I/O port configuration.

4.6

AC measurement conditions

Table 10. AC measurement conditions

TA = −40 to 105 °C (for the 3.3 V voltage range only) and TA = −25 to 85 °C (for the 1.8 V and 3.3 V voltage ranges).

f = 1 MHz, unless otherwise specified.

Parameter

Value (1)

Input rise and fall times

10 ns max

Input pulse voltage

VIL to VIH

Input timing reference voltage

0.5 × VPS

Output timing reference voltage

VOL to VOH

1. Measurement points are at CMOS levels: 0.3 × VPS and 0.7 × VPS.

Figure 9. AC testing input/output waveforms

VIH

VIL

VOH

VOL

Output

Input

0.5 VCC

ST33TPHF2XSPI

AC measurement conditions

DS14186 - Rev 1

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