3

Serial peripheral interface (SPI) and TPM registers

The SPI interface implemented in this device complies with the TCG PC Client-specific TPM Platform

specifications [PTP 2.0 r1.05] for the TPM 2.0 library.

The SPI supports only one clock mode (CPOL=0, CPHA=0).

Data is transferred serially between master and slave; the most significant bit (msb) first, least significant bit (lsb)

last.

Addresses and commands are transferred msb first for the entire field, e.g. the 24-bit address is transferred by

sending b23 first, then b22 all the way up to b0.

The TPM drives data on the falling edge of the SPI clock.

The TPM samples data on the rising edge of the SPI clock.

The TPM will always decode a 24-bit address in the 0xD4_xxxx range when the TPM's SPI_CS pin is asserted.

The ST33TPHF2XSPI supports an interrupt interface line directly from the TPM to the main platform MCU. This

interrupt is supported using a dedicated GPIO (SPI_PIRQ, active low). The device detects a change in the TPM

status when the TPM triggers a falling edge on pin SPI_PIRQ.

3.1

SPI communication protocol flow control

3.1.1

SPI communication

The TPM flow control mechanism operates on a transaction basis and can transfer data of various sizes. The

TPM can transfer or receive 1 up to 32 bytes of data per transaction.

Because the SPI does not support any acknowledge signal, a specific way to synchronize between the host and

the TPM has been defined.

In order to synchronize the start of a command, the SPI master must set low the SPI_CS pin when sending a

command and set the SPI_CS pin back to high at the end of the transaction.

An SPI start of frame is detected when the SPI_CS signal goes low. This causes the TPM to drive the SPI_MISO

signal low. An end of frame is detected when the SPI_CS line goes to the high voltage level.

The transmit sequence begins when the TPM receives the SPI_CLK signal, the SPI_CS signal goes low and the

most significant bit of the data is present on the SPI_MOSI pin.

Figure 2. SPI transmit sequence

SPI_MISO

SPI_CS

SPI_CLK

SPI_MOSI

SPI_MISO

SPI_MISO

SPI_MOSI

SPI_MOSI

The TPM host initiates every command by transmitting a single byte on the SPI_MOSI pin that tells the TPM if

it is a read or write operation in a register. This byte also contains the size of the transfer including the 1st byte.

The command processing continues with the transfer of three more bytes containing the address of the targeted

register.

At this time, depending on the targeted register, the TPM is able to insert 1 or more Wait states before

acknowledging the transfer. A Wait state is a Low state (0) sent on the SPI_MISO pin by the TPM. An

Acknowledgment is a byte, whose last bit is ‘1’, sent on the SPI_MISO pin by the TPM.

In the case of a register read command, the TPM sends on the SPI_MISO pin the number of requested bytes

from the requested register.

ST33TPHF2XSPI

Serial peripheral interface (SPI) and TPM registers

DS14186 - Rev 1

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