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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TSB41AB2PAPR датащи(PDF) 14 Page - Texas Instruments |
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TSB41AB2PAPR датащи(HTML) 14 Page - Texas Instruments |
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14 / 50 page  TSB41AB2, TSB41AB2I IEEE 1394a2000 TWOPORT CABLE TRANSCEIVER/ARBITER SLLS424G − JUNE 2000 − REVISED DECEMBER 2004 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 thermal characteristics PARAMETER TEST CONDITIONS† MIN TYP MAX UNIT RθJA Junction-to-ambient thermal resistance Board mounted, no air flow, high conductivity TI-recommended test board, chip soldered or 26 °C/W RθJC Junction-to-case-thermal resistance TI-recommended test board, chip soldered or greased to thermal land with 1 oz. copper 5.9 °C/W RθJA Junction-to-ambient thermal resistance Board mounted, no air flow, high conductivity TI-recommended test board with thermal land, but no 58.57 °C/W RθJC Junction-to-case thermal resistance TI-recommended test board with thermal land, but no solder or grease thermal connection to thermal land with 1 oz. copper 5.9 °C/W RθJA Junction-to-ambient thermal resistance Board mounted, no air flow, low conductivity JEDEC 60.08 °C/W RθJC Junction-to-case thermal resistance Board mounted, no air flow, low conductivity JEDEC test board with 1 oz. copper 5.9 °C/W † Use of thermally enhanced PowerPad PAP package is assumed in all three test conditions. switching characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Jitter, transmit Between TPA and TPB ±0.15 ns Skew, transmit Between TPA and TPB ±0.1 ns th Hold time, CTL0, CTL1, D0 – D7, LREQ after SYSCLK 50% to 50%, See Figure 2 2 ns tsu Setup time, CTL0, CTL1, D0 – D7, LREQ to SYSCLK 50% to 50%, See Figure 2 5 ns td Delay time, SYSCLK to CTL0, CTL1, D0 – D7 50% to 50%, See Figure 3 2‡ ns tr TP differential rise time, transmit 10% to 90%, at 1394 connector 0.5 1.2 ns tf TP differential fall time, transmit 90% to 10%, at 1394 connector 0.5 1.2 ns ‡ Test Conditions: 3.3 VCC, TA = 25°C |
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