TSB41AB2PAPR datasheet(40/50 Pages) TI

40 / 50 page

TSB41AB2, TSB41AB2I

IEEE 1394a2000 TWOPORT CABLE

TRANSCEIVER/ARBITER

SLLS424G − JUNE 2000 − REVISED DECEMBER 2004

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

transmit (continued)

After sending the last packet for the current bus ownership, the LLC releases the bus by asserting idle on the

CTL terminals for two clock cycles. The PHY begins asserting idle on the CTL terminals one clock after sampling

idle from the link. Note that whenever the D and CTL terminals change direction between the PHY and the LLC,

there is an extra clock period allowed so that both sides of the interface can operate on registered versions of

the interface signals. Figure 20 is the transmission timing diagram for normal packets, and Figure 21 is the

transmission timing diagram for cancelled or null packets.

(6)

(7)

(5)

(4)

(3)

(2)

(1)

SPD

D0–D7

CTL0, CTL1

SYSCLK

Link Controls CTL and D

PHY CTL and D Outputs Are High Impedance

NOTE: SPD = Speed code, see Table 20

d0 − dn = Packet data

Figure 20. Normal Packet Transmission Timing

The sequence of events for a normal packet transmission is as follows:

Transmit operation initiated. The PHY asserts grant on the CTL lines followed by idle to hand over control

of the interface to the link so that the link may transmit a packet. The PHY releases control of the interface

(that is, it places its CTL and D outputs in a high-impedance state) following the idle cycle.

Optional idle cycle. The link may assert at most one idle cycle preceding assertion of either hold or transmit.

This idle cycle is optional; the link is not required to assert idle preceding either hold or transmit.

Optional hold cycles. The link may assert hold for up to 47 cycles preceding assertion of transmit. These

hold cycle(s) are optional; the link is not required to assert hold preceding transmit.

Transmit data. When data is ready to be transmitted, the link asserts transmit on the CTL lines along with

the data on the D lines.

Transmit operation terminated. The transmit operation is terminated by the link asserting hold or idle on the

CTL lines. The link asserts hold to indicate that the PHY is to retain control of the serial bus in order to

transmit a concatenated packet. The link asserts idle to indicate that packet transmission is complete and

the PHY may release the serial bus. The link then asserts idle for one more cycle following this cycle of hold

or idle before releasing the interface and returning control to the PHY.

Concatenated packet speed code. If multispeed concatenation is enabled in the PHY, the link asserts a

speed code on the D lines when it asserts hold to terminate packet transmission. This speed code indicates

the transmission speed for the concatenated packet that is to follow. The encoding for this concatenated

packet speed code is the same as the encoding for the received packet speed code (see Table 20). The

link may not concatenate an S100 packet onto any higher-speed packet.

After regaining control of the interface, the PHY asserts at least one cycle of idle before any subsequent

status transfer, receive operation, or transmit operation.

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