TSB41AB2PAPR datasheet(41/50 Pages) TI

41 / 50 page

TSB41AB2, TSB41AB2I

IEEE 1394a2000 TWOPORT CABLE

TRANSCEIVER/ARBITER

SLLS424G − JUNE 2000 − REVISED DECEMBER 2004

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

transmit (continued)

(5)

(4)

(3)

(2)

(1)

D0–D7

CTL0, CTL1

SYSCLK

Link Controls CTL and D

PHY CTL and D Outputs Are High Impedance

Figure 21. Cancelled/Null Packet Transmission

The sequence of events for a cancelled/null packet transmission is as follows:

Transmit operation initiated. PHY asserts grant on the CTL lines followed by idle to hand over control of the

interface to the link.

Optional idle cycle. The link may assert at most one idle cycle preceding assertion of hold. This idle cycle

is optional; the link is not required to assert idle preceding hold.

Optional hold cycles. The link may assert hold for up to 47 cycles preceding assertion of idle. These hold

cycle(s) are optional; the link is not required to assert hold preceding Idle.

Null transmit termination. The null transmit operation is terminated by the link asserting two cycles of idle

on the CTL lines and then releasing the interface and returning control to the PHY. Note that the link may

assert idle for a total of three consecutive cycles if it asserts the optional first idle but does not assert hold.

(It is recommended that the link assert three cycles of idle to cancel a packet transmission if no cycles of

hold are asserted. This ensures that either the link or PHY controls the interface in all cycles.)

After regaining control of the interface, the PHY asserts at least one cycle of idle before any subsequent

status transfer, receive operation, or transmit operation.

interface reset and disable

The LLC controls the state of the PHY-LLC interface using the LPS signal. The interface may be placed into a

reset state, a disabled state, or be made to initialize and then return to normal operation. When the interface

is not operational (whether reset, disabled, or in the process of initialization) the PHY cancels any outstanding

bus request or register read request, and ignores any requests made via the LREQ line. Additionally, any status

information generated by the PHY is not queued, and thus does not cause a status transfer upon restoration

of the interface to normal operation.

The LPS signal may be either a level signal or a pulsed signal, depending upon whether the PHY-LLC interface

is a direct connection or is made across an isolation barrier. When an isolation barrier exists between the PHY

and LLC (whether of the TI bus-holder type or Annex J type) the LPS signal must be pulsed. In a direct

connection, the LPS signal may be either a pulsed or a level signal. Timing parameters for the LPS signal are

given in Table 21.

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