ADF4252BCP datasheet(25/28 Pages) AD

25 / 28 page

REV. B

ADF4252

–25–

±100 kHz from the RF carrier. Harmonics of all spurs mentioned

will also appear. With the lowest spur setting enabled, the spurs

will be attenuated into the noise floor.

Prescaler

The prescaler limits the INT value. With P = 4/5, Nmin = 31.

With P = 8/9, Nmin = 91.

The prescaler can also influence the phase noise performance.

If INT < 91, a prescaler of 4/5 should be used. For applications

where INT > 91, P = 8/9 should be used for optimum noise

performance.

Filter Design—ADIsimPLL

A filter design and analysis program is available to help users

implement their PLL design. Visit www.analog.com/pll for a

free download of the ADIsimPLL software. The software

designs, simulates, and analyzes the entire PLL frequency

domain and time domain response. Various passive and active

filter architectures are allowed.

INTERFACING

The ADF4252 has a simple SPI compatible serial interface for

writing to the device. SCLK, SDATA, and LE control the data

transfer. When LE (latch enable) goes high, the 24 bits that have

been clocked into the input register on each rising edge of SCLK

will be transferred to the appropriate latch. See Figure 1 for the

Timing Diagram and Table I for the Control Bit Truth Table.

The maximum allowable serial clock rate is 20 MHz, which

means that the maximum update rate possible for the device is

833 kHz or one update every 1.2

µs. This is certainly more than

adequate for systems that will have typical lock times in hun-

dreds of microseconds.

ADuC812

ADF4252

SCLK

SDATA

MUXOUT

(LOCK DETECT)

SCLOCK

MOSI

I/O PORTS

Figure 8. ADuC812 to ADF4252 Interface

ADuC812 Interface

Figure 8 shows the interface between the ADF4252 and the

ADuC812 microconverter. Since the ADuC812 is based on

an 8051 core, this interface can be used with any 8051 based

microcontroller. The microconverter is set up for SPI master

mode with CPHA = 0. To initiate the operation, the I/O port

driving LE is brought low. Each latch of the ADF4252 needs

(at most) a 24-bit word. This is accomplished by writing three

8-bit bytes from the microconverter to the device. When the third

byte has been written, the LE input should be brought high to

complete the transfer.

I/O port lines on the ADuC812 are also used to control power-

down (CE input) and to detect lock (MUXOUT configured as

lock detect and polled by the port input).

When operating in the mode described, the maximum SCLOCK

rate of the ADuC812 is 4 MHz. This means that the maximum

rate at which the output frequency can be changed will be 166 kHz.

ADSP-21xx

ADF4252

SCLK

SDATA

MUXOUT

(LOCK DETECT)

SCLK

I/O FLAGS

TFS

Figure 9. ADSP-21xx to ADF4252 Interface

ADSP-2181 Interface

Figure 9 shows the interface between the ADF4252 and the

ADSP-21xx digital signal processor. Each latch of the ADF4252

needs (at most) a 24-bit word. The easiest way to accomplish this

using the ADSP-21xx family is to use the autobuffered transmit

mode of operation with alternate framing. This provides a means

for transmitting an entire block of serial data before an interrupt is

generated. Set up the word length for eight bits and use three memory

locations for each 24-bit word. To program each 24-bit latch, store

the three 8-bit bytes, enable the autobuffered mode, and then write

to the transmit register of the DSP. This last operation initiates the

autobuffer transfer.

PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE

The leads on the chip scale package (CP-24) are rectangular. The

printed circuit board pad for these should be 0.1 mm longer than

the package land length and 0.05 mm wider than the package land

width. The land should be centered on the pad. This will ensure

that the solder joint size is maximized.

The bottom of the chip scale package has a central thermal pad.

The thermal pad on the printed circuit board should be at least

as large as this exposed pad. On the printed circuit board, there

should be a clearance of at least 0.25 mm between the thermal

pad and the inner edges of the pad pattern. This will ensure that

shorting is avoided.

Thermal vias may be used on the printed circuit board thermal pad

to improve thermal performance of the package. If vias are used,

they should be incorporated in the thermal pad at 1.2 mm pitch

grid. The via diameter should be between 0.3 mm and 0.33 mm,

and the via barrel should be plated with 1 oz copper to plug the via.

The user should connect the printed circuit board to AGND.

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