ADF4252BCP datasheet(24/28 Pages) AD

24 / 28 page

REV. B

–24–

ADF4252

So, from Equation 5:

FMHz

PFD =×

=×









MHz

. GHz

MHz

INT +

FRAC

where INT = 138 and FRAC = 30.

IF Synthesizer: An Example

The IF synthesizer should be programmed as follows:

OUT

PFD

=×

()+

[]×

(6)

where IFOUT = the output frequency of external voltage controlled

oscillator (VCO), P = the IF prescaler, B = the B counter value,

and A = the A counter value.

Equation 5 applies in this example as well.

For example, in a GSM1800 system, where 540 MHz IF fre-

quency output (IFOUT) is required, a 13 MHz reference frequency

input (REFIN) is available and a 200 kHz channel resolution

(FRES) is required on the IF output. The prescaler is set to 16/17.

IF REFIN doubler is disabled.

By Equation 5,

200

kHz

MHz

=×

if R = 65.

By Equation 6,

540

200

MHz

kHz

=×

()+

[]

if B = 168 and A = 12.

Modulus

The choice of modulus (MOD) depends on the reference signal

(REFIN) available and the channel resolution (FRES) required at

the RF output. For example, a GSM system with 13 MHz

REFIN would set the modulus to 65. This means that the RF

output resolution (FRES) is the 200 kHz (13 MHz/65) necessary

for GSM.

Reference Doubler and Reference Divider

There is a reference doubler on-chip, which allows the input

reference signal to be doubled. This is useful for increasing the

PFD comparison frequency. Making the PFD frequency higher

improves the noise performance of the system. Doubling the

PFD frequency will usually result in an improvement in noise

performance of 3 dB. It is important to note that the PFD can-

not be operated above 30 MHz due to a limitation in the speed

of the

circuit of the N divider.

12-Bit Programmable Modulus

Unlike most other fractional-N PLLs, the ADF4252 allows the

user to program the modulus over a 12-bit range. This means

that the user can set up the part in many different configurations

for a specific application, when combined with the reference

doubler and the 4-bit R counter.

For example, in an application that requires 1.75 GHz RF and

200 kHz channel step resolution, the system has a 13 MHz

reference signal.

One possible setup is feeding the 13 MHz directly to the PFD

and programming the modulus to divide by 65. This results in

the required 200 kHz resolution.

Another possible setup is using the reference doubler to create

26 MHz from the 13 MHz input signal. This 26 MHz is then

fed into the PFD. The modulus is now programmed to divide by

130, which also results in 200 kHz resolution. This offers supe-

rior phase noise performance over the previous setup.

The programmable modulus is also very useful for multistandard

applications. If a dual-mode phone requires PDC and GSM1800

standards, the programmable modulus is a huge benefit. PDC

requires 25 kHz channel step resolution, whereas GSM1800

requires 200 kHz channel step resolution. A 13 MHz reference

signal could be fed directly to the PFD. The modulus would

then be programmed to 520 when in PDC mode (13 MHz /520 =

25 kHz). The modulus would be reprogrammed to 65 for

GSM1800 operation (13 MHz/65 = 200 kHz). It is important

that the PFD frequency remains constant (13 MHz). This allows

the user to design one loop filter that can be used in both setups

without any stability issues. It is the ratio of the RF frequency to

the PFD frequency that affects the loop design. Keeping this

relationship constant, and instead changing the modulus factor,

results in a stable filter.

Spurious Optimization and Fastlock

As mentioned in the Noise and Spur Setting section, the part can

be optimized for spurious performance. However, in fastlocking

applications, the loop bandwidth needs to be wide. Therefore,

the filter does not provide much attenuation of the spurious. The

programmable charge pump can be used to avoid this issue. The

filter is designed for a narrow-loop bandwidth so that steady-state

spurious specifications are met. This is designed using the low-

est charge pump current setting. To implement fastlock during

a frequency jump, the charge pump current is set to the maxi-

mum setting for the duration of the jump. This has the effect of

widening the loop bandwidth, which improves lock time. When the

PLL has locked to the new frequency, the charge pump is again

programmed to the lowest charge pump current setting. This

will narrow the loop bandwidth to its original cutoff frequency

to allow for better attenuation of the spurious than the wide-loop

bandwidth.

Spurious Signals—Predicting Where They Will Appear

Just as in integer-N PLLs, spurs will appear at PFD frequency

offsets on either side of the carrier (and multiples of the PFD

frequency). In a fractional-N PLL, spurs will also appear at

frequencies equal to the RFOUT channel step resolution (FRES).

The ADF4252 uses a high order fractional interpolator engine,

which results in spurs also appearing at frequencies equal to

half of the channel step resolution. For example, examine the

GSM1800 setup with a 26 MHz PFD and 200 kHz resolution.

Spurs will appear at

±26 MHz from the RF carrier (at an

extremely low level due to filtering). Also, there will be spurs at

±200 kHz from the RF carrier. Due to the fractional interpolator

architecture used in the ADF4252, spurs will also appear at

ADF4252BCP датащи(PDF) 24 Page - Analog Devices

ADF4252BCP датащи(HTML) 24 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

датащи скачать

ссылки URL