ADF4252BCP datasheet(12/28 Pages) AD

12 / 28 page

REV. B

–12–

ADF4252

Phase Frequency Detector (PFD) and Charge Pump

The PFD takes inputs from the R counter and N counter and

produces an output proportional to the phase and frequency

difference between them. Figure 6 is a simplified schematic. The

antibacklash pulse. This pulse ensures that there is no dead zone

in the PFD transfer function and minimizes phase noise and

reference spurs.

+IN

CLR1

DELAY

ELEMENT

CLR2

DOWN

CHARGE

PUMP

–IN

Figure 6. PFD Simplified Schematic

MUXOUT and Lock Detect

The output multiplexer on the ADF4252 allows the user to

access various internal points on the chip. The state of MUXOUT

is controlled by M4, M3, M2, and M1 in the master register.

Table I shows the full truth table. Figure 7 shows the MUXOUT

section in block diagram format.

LOGIC LOW

IF ANALOG LOCK DETECT

IF R DIVIDER OUTPUT

IF N DIVIDER OUTPUT

RF ANALOG LOCK DETECT

IF/RF ANALOG LOCK DETECT

IF DIGITAL LOCK DETECT

LOGIC HIGH

RF R DIVIDER OUTPUT

RF N DIVIDER OUTPUT

THREE STATE OUTPUT

RF DIGITAL LOCK DETECT

RF/IF DIGITAL LOCK DETECT

LOGIC HIGH

LOGIC LOW

MUX

CONTROL

MUXOUT

DVDD

DGND

Figure 7. MUXOUT Circuit

Lock Detect

MUXOUT can be programmed for two types of lock detect: digital

and analog. Digital is active high. The N-channel open-drain

analog lock detect should be operated with an external pull-up

resistor of 10 k

Ω nominal. When lock has been detected, this

output will be high with narrow low going pulses.

Input Shift Register

Data is clocked in on each rising edge of CLK. The data is

clocked in MSB first. Data is transferred from the input register

to one of seven latches on the rising edge of LE. The destination

latch is determined by the state of the three control bits (C2, C1,

and C0) in the shift register. These are the three LSBs: DB2,

DB1, and DB0, as shown in Figure 1. The truth table for these

bits is shown in Table I. Table II summarizes how the registers

are programmed.

Table I. Control Bit Truth Table

Data Latch

000

RF N Divider Reg

001

RF R Divider Reg

010

RF Control Reg

011

Master Reg

100

IF N Divider Reg

101

IF R Divider Reg

110

IF Control Reg

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