EM6821 datasheet(31/68 Pages) EMMICRO

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EM6821

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8. 10-bit Counter

The EM6821 has a built-in universal cyclic counter. It can be configured as 10, 8, 6 or 4-bit counter. If 10-bits

are selected we call that full bit counting, if 8, 6 or 4-bits are selected we call that limited bit counting.

The counter works in up- or down count mode. Eight clocks can be used as the input clock source, six of them

are prescaler frequencies and two are coming from the input pads PA[0] and PA[3]. In this case the counter

can be used as an event counter.

The counter generates an interrupt request IRQCount0 every time it reaches 0 in down count mode or 3FF in

up count mode. Another interrupt request IRQCntComp is generated in compare mode whenever the counter

value matches the compare data register value. Each of this interrupt requests can be masked (default). See

section 10 for more information about the interrupt handling.

A 10-bit data register CReg[9:0] is used to initialize the counter at a specific value (load into Count[9:0]). This

data register (CReg[9:0]) is also used to compare its value against Count[9:0] for equivalence.

A Pulse-Width-Modulation signal (PWM) can be generated and output on port B terminal PB[3].

8.1 Full and Limited Bit Counting

In Full Bit Counting mode the counter uses its maximum

of 10-bits length (default ). With the BitSel[1,0] bits in

for IRQ generation, to 8, 6 or 4 bits. This means that

actually the counter always uses all the 10-bits, but

IRQCount0 generation is only performed on the number

of selected bits. The unused counter bits may or may not be taken into account for the IRQComp generation

depending on bit SelIntFull. Refer to chapter 8.4.

Figure 22. 10-bit Counter Block Diagram

Comparator

Up/Down

Up/Down Counter

EvCount

Counter Read Register

RegCDataL, M, H

(Count[9:0])

RegCDataL, M, H (CReg[9:0])

Load

IRQCntComp

PWM

IRQCount0

Data Register

DB[3:0]

PA[0]

Ck[15]

Ck[12]

Ck[10]

Ck[8]

Ck[4]

Ck[1]

PA[3]

MUX

RegCCntl1, 2

CountFSel2...0

Up/Down

Start

EvCount

Load

EnComp

Table 7.3.1. Counter length selection

BitSel[1]

BitSel[0 ]

counter length

10-Bit

8-Bit

6-Bit

4-Bit

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