EM6821 datasheet(20/68 Pages) EMMICRO

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EM6821

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6.6 Port Serial

The EM6821 contains a simple, half duplex three wire synchronous type serial interface., which can be used to

program or read an external EEPROM, ADC, ... etc.

For data reception, a shift-register converts the serial input data on the SIN(PSP[0]) terminal to a parallel

format, which is subsequently read by the CPU in registers RegSDataL and RegSDataH for low and high

nibble. To transmit data, the CPU loads data into the shift register, which then serializes it on the

SOUT(PSP[2]) terminal.

It is possible for the shift register to simultaneously shift data out on the SOUT

terminal and shift data on the SIN terminal. In Master mode, the shifting clock is supplied internally by the

Prescaler : one of three prescaler frequencies are available, Ck[16], Ck[15] or Ck[14]. In Slave mode, the

shifting clock is supplied externally on the SCLKIn(PSP[3]) terminal. In either mode, it is possible to program :

the shifting edge, shift MSB first or LSB first and direct shift output. All these selection are done in register

RegSCntl1 and RegSCntl2.

The PSP[3..0] terminal configuration is shown in Figure 14. When the Serial Interface is active then :

∗ PSP[1] {Ready / CS) is outputting the ready (slave mode) or the CS signal (master mode).

∗ PSP[2] {SOUT} is always an output.

∗ PSP[0] {SIN} is always an input.

∗ PSP[3] {SCLK} is an output for Master mode {SCLKOut} and an input for Slave mode {SCLKIn}

6.6.1 4-bit Parallel I/O

Selecting OM[1],OM[0] = ‘1’ in register RegSCntl2 the PSP[3:0] terminals are configured as a 4-bit Output.

Output data is stored in the register RegSPData .

The RegSPData is defined as a read/write register, but what is read is not the register output, but the port

PSP[3:0] terminal values

Selecting OM[1],OM[0] = ‘0’ in register RegSCntl2 the PSP[3:0] outputs are cut off (tristate). The terminals

can be used as inputs with individual (bit-wise) pull-up or pull-down settings.

Independent of the selected configuration, the PSP[3:0] terminal levels are always readable.

Figure 13. Serial Interface Architecture

Shift Complete

(8th Shift Clock)

8 Bit Shift Register

Serial Input Data

from SIN

term inal

IRQSerial

Serial Output Data

to SOUT Terminal

Serial Master Clock Output

SCLKOut to SCLK Terminal

Internal Master Clock Source

(from Prescaler)

External Slave Clock Source

(SCLKIn from SCLK terminal)

Mode

Start

Direct

MSB/LSB

Status

Shift

First

Control Logic

Clock

Enable

Shift CK

Status to

CS/ Ready

Terminal

Control

Status

Registers

Reset

Start

W rite

Read

4-Bit Internal Data Bus

High-Z to all

SP[3:0] Terminals

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