EM6821 datasheet(42/68 Pages) EMMICRO

42 / 68 page

EM6821

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Any interrupt request sent by a periphery cell while the corresponding mask is not set will not be stored in the

interrupt request register. All interrupt requests are stored in their IRQxx registers depending only on their

mask setting and not on the general interrupt enable status.

Whenever the EM6821 goes into halt mode the IntEn bit is automatically set to 1, thus allowing to resume from

halt mode with an interrupt.

10.1 Interrupt Control Registers

Table 10.1.6 Register RegIRQ1

Bit

Name

Reset

R/W

Description

IRQPA[3]

R *

Port A PA[3] interrupt request

IRQPA[2]

R *

Port A PA[2] interrupt request

IRQPA[1]

R *

Port A PA[1] interrupt request

IRQPA[0]

R *

Port A PA[0] interrupt request

*; Writing of 1 clears the corresponding bit.

Table 10.1.7 Register RegIRQ2

Bit

Name

Reset

R/W

Description

IRQHz1

R *

Prescaler interrupt request

IRQHz32/8

R *

Prescaler interrupt request

IRQBlink

R *

Prescaler interrupt request

IRQBz

R *

Melody timer interrupt request

*; Writing of 1 clears the corresponding bit.

Table 10.1.8 Register RegIRQ3

Bit

Name

Reset

R/W

Description

IRQSerial

R *

Serial interrupt request

IRQMSC

R *

Millisecond counter int. request

IRQCount0

R *

Counter interrupt request

IRQCntComp

R *

Counter interrupt request

*; Writing of 1 clears the corresponding bit.

Table 10.1.9 Register RegIRQMask1

Bit

Name

Reset

R/W

Description

MaskIRQPA[3]

R/W

Port A PA[3] interrupt mask

MaskIRQPA[2]

R/W

Port A PA[2] interrupt mask

MaskIRQPA[1]

R/W

Port A PA[1] interrupt mask

MaskIRQPA[0]

R/W

Port A PA[0] interrupt mask

Interrupt is not stored if the mask bit is 0.

Table 10.1.10 Register RegIRQMask2

Bit

Name

Reset

R/W

Description

MaskIRQHz1

R/W

Prescaler interrupt mask

MaskIRQHz32/8

R/W

Prescaler interrupt mask

MaskIRQBlink

R/W

Prescaler interrupt mask

MaskIRQBz

R/W

Melody timer interrupt mask

Interrupt is not stored if the mask bit is 0.

Table 10.1.11 Register RegIRQMask3

Bit

Name

Reset

R/W

Description

MaskIRQSerial

R/W

Serial interrupt mask

MaskIRQMSC

R/W

Millisecond counter int. mask

MaskIRQCount0

R/W

Counter interrupt mask

MaskIRQCntComp

R/W

Counter interrupt mask

Interrupt is not stored if the mask bit is 0

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