LTC4331 datasheet(18/22 Pages) AD

18 / 22 page

LTC4332

Rev. A

For more information www.analog.com

PCB Layout

A ground plane layout is recommended. A 4.7μF bypass

capacitor should be placed no more than 7mm away from

the VCC pin. The PC board traces connected to signal pairs

(Y, Z) and (A, B) should be symmetrical and as short

as possible to maintain good differential signal integrity.

Route the differential signals pairs (Y, Z) and (A, B) as

an edge coupled microstrip with a differential impedance

approximately matching the cable impedance.

Link Termination and Biasing

To minimize the transmission line reflections over the

link, a termination resistor should be connected between

pins A and B at each node. Each resistor’s value should

closely match the characteristic impedance of the differ-

ential cable to reduce reflections. A bias resistor net-work

should also be inserted at each node to maintain the idle

state when the drivers are disabled. Select RB and RT2

such that 200Ω ≤ RB ≤ 620Ω and 100Ω ≤ RT2 ≤ 110Ω.

See Figure 15.

Auxiliary Protection for 5kV Surge, 5kV EFT, and 30kV

IEC ESD

An interface transceiver used in an industrial setting

may be exposed to extremely high levels of electrical

overstress due to phenomena such as lightning surge,

electrical fast transient (EFT) from switching high cur-

rent inductive loads, and electrostatic discharge (ESD)

from the discharge of electrically charged personnel or

equipment. The LTC4332 is designed for high robustness

against ESD and EFT, but the on-chip protection is not

able to absorb the energy associated with the 61000-4-5

surge transients. Therefore, a properly designed external

protection network is necessary to achieve a high level

of surge protection, and can also extend the ESD and EFT

performance of the LTC4332 to extremely high levels.

Refer to section Auxiliary Protection for IEC Surge, EFT

and ESD on page 16 of Analog Devices LTC2864 data

sheet for a detailed description and diagram of the exter-

nal protection network.

The network provides the following protection:

• EC 61000-4-2 ESD Level 4: ±30kV contact, ±30kV air

(line to GND, direct discharge to bus pins with trans-

ceiver and protection circuit mounted on a ground ref-

erenced test card per Figure 4 of the standard)

• IEC 61000-4-4 EFT Level 4: ±5kV (line to GND, 5kHz

repetition rate, 15ms burst duration, 60 second test

duration, discharge coupled to bus pins through 100pF

capacitor per paragraph 7.3.2 of the standard)

• IEC 61000-4-5 Surge Level 4: ±5kV (line to GND, line to

line, 8/20μs waveform, each line coupled to generator

through 80Ω resistor per Figure 14 of the standard)

APPLICATIONS INFORMATION

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