LTC4332

15

Rev. A

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APPLICATIONS INFORMATION

an EVENT is triggered and its corresponding INT_EN bit

is set high, INT is driven low. To clear the interrupt set

the triggered event or the corresponding event enable bit

to 0. Note that local INT could continue to be low due to

a low value from a remote INT pin.

SPI Timeout

On the remote side, the LTC4332 acting as a SPI master

resets the SPI bus if any slave select pin exceeds time

tTIMEOUT:MASTER. with the remote SCK inactive. This pre-

vents the remote SPI bus from getting stuck active in the

event of lost or corrupted link data during a trans fer.

Remote Reset

The local side LTC4332 can trigger a remote side LTC4332

reset by holding the ON pin low for a minimum of tREMOTE_

RESET. In addition, the remote LTC4332 is automatically

reset after tREMOTE_RESET if the link is disconnected. A

remote reset disables all remote side outputs until link

communication is reestablished.

Link Speed

The link baud rate is set using the SPEED1 and SPEED2

pins as shown in Table 2. The local SCK frequency cannot

exceed the maximum SCK frequency for a given SPEED

INDEX. The SPEED INDEX must be set to the same value

on each side of the link.

Control Interface

The LTC4332 provides a separate slave select pin, SSC,

that allows a user to access the internal control interface

for configuration and monitoring. The interface supports

SPI modes (0,0) and (1,1) only. Read and write accesses

are shown in Figure 13 and Figure 14. The bit order is

MSB first. The first byte includes the register address

in bits <7-1> and a read(1)/write(0) bit in the LSB. Only

single data byte accesses per transfer are supported.

Programmed values are retained while VCC ≥ 3.0V

An optional CRC byte can be appended to a write transfer.

The CRC byte is calculated as a CRC-8 checksum over

the first two bytes in the packet. The polynomial used

is x8 + x2 + x + 1 initialized to zero. If the CRC byte is

incomplete or incorrect, the LTC4332 will not commit the

write transfer into the internal registers. Additionally, the

fault bit SPI_WRITE_FAULT is asserted and local INT pin

drives low if enabled.

The CRC byte is also available in a read transfer. In this

case the CRC byte is calculated over the first byte written

on the MOSI pin and the data byte read on the MISO pin.

Use of the CRC byte is recommended in high noise envi-

ronments or high reliability systems.

Table 2. Link Speed

SPEED1

(NOTE 1)

SPEED2

(NOTE 1)

SPEED INDEX

SPEED FACTOR

(NOTE 2)

MAX SCK FREQUENCY (kHz)

MAX CABLE LENGTH (m)

(NOTE 3)

L

L

8

1×

2000

30

Float

L

7

2×

1000

60

H

L

6

4×

500

150

L

Float

5

8×

250

250

Float

Float

4

16×

125

500

L

H

3

24×

83

750

H

Float

2

32×

63

1000

Float

H

1

64×

31

1200

H

H

0

80×

25

1200+

Note 1. For assignments to Float, 0.5 • VL can also be applied to pin.

Note 2. Used for some switching parameter calculations.

Note 3. Evaluated with CAT5E Ethernet cable in a lab environment. Actual maximum cable length depends on type of cable and application environment.