LTC4331 datasheet(12/22 Pages) AD

12 / 22 page

LTC4332

Rev. A

For more information www.analog.com

APPLICATIONS INFORMATION

Overview

Two LTC4332 devices are required for a complete extended

SPI network. On the local side, set the REMOTE pin low

to set the SPI interface into slave device mode. A second

LTC4332 with its REMOTE pin set high sets the SPI inter-

face into master device mode. Three slave select pins are

available to connect to slave devices on the remote side

along with a shared interrupt signal.

The LTC4332 SPI extender solution supports remote slave

devices with mixed SCK polarity and phase requirements.

The remote side LTC4332 switches to the device’s specific

SPI interface mode before initiating a transfer.

Using an integrated high-performance differential trans-

ceiver for link communication, a local SPI master can

access remote slave devices up to 1200m using inexpen-

sive CAT5 or other differential-pair type cabling.

The LTC4332 SPI extender solution can be inserted

into an existing SPI network with minimal impact. Write

accesses to remote slave devices are software transpar-

ent; however, read accesses from remote slaves incur a

one-word latency.

driven low, slave select pins SS1, SS2, SS3 are available

to access remote SPI slave devices. The device captures

SPI data on the MOSI pin and sends it across the first dif-

ferential link as an encoded bit-stream to the remote side

LTC4332. Concurrently, the local side LTC4332 receives

read-back data from the remote side through the second

differential pair and stores it in an internal word FIFO.

Read data is held in the internal word FIFO until the next

word boundary is detected then is driven onto pin MISO.

Therefore, MISO data is always delayed by one word. See

Figure 12. An extra word appended to the existing trans-

action can be used to read out the last word. The word

length defaults to 8 bits. Words lengths from 8 to 32 bits

are supported by writing the WORD_LENGTH register

in the control interface using SSC. The internal FIFO is

always flushed at the start of transaction.

The SPI protocol supports four unique timing configura-

tions defined by the SCK polarity (CPOL) and clock phase

(CPHA) summarized in Table 1.

Table 1. SPI Mode

CPOL

CPHA

SCK IDLE

DATA CAPTURED

DATA LAUNCHED

Low

Rising SCK

Falling SCK

Low

Falling SCK

Rising SCK

High

Falling SCK

Rising SCK

High

Rising SCK

Falling SCK

Figure 10. LTC4332 Solution Inserted Into a SPI Network

Figure 11. SPI Mode Waveform

Local Mode

The LTC4332 is in slave SPI mode when the REMOTE

pin is set low. Pins SCK and MOSI are inputs while pin

MISO is an output. Once the link status output pin LINK is

When set to local mode, the LTC4332 SPI slave interface

supports SPI modes (0,0) and (1,1) where (CPOL, CPHA).

The maximum SCK frequency is limited by fSCK:SLAVE and

Table 2 when accessing remote SPI slaves. The MISO

pin is weakly held to the previously driven value when

all slave select pins are high. MISO is only driven after a

CAPTURE

LAUNCH

4332 F11

SCK

(CPOL = 0)

SCK

(CPOL = 1)

MOSI, MISO

(CPHA = 0)

MOSI, MISO

(CPHA = 1)

LAUNCH

CAPTURE

REM_SCK

REM_MOSI

REM_MISO

REM_SS

MCU_SCK

MCU_MOSI

MCU_MISO

MCU_SS

SCK

MOSI

MISO

µP

LTC4332

DEVICE

REMOTE

µP

DEVICE

TWISTED

PAIR

LOCAL SIDE

REMOTE SIDE

BREAK CONNECTIONS AND INSERT LTC4332 SOLUTION

LOCAL SLAVE

LOCAL MASTER

LOCAL

SLAVE

LOCAL

MASTER

REMOTE

MASTER

REMOTE

SLAVE

LOCAL

SPI BUS

REMOTE

SPI BUS

V L

MCU_INT

REM_INT

INT

4332 F10

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