LTC4331 datasheet(14/22 Pages) AD

14 / 22 page

LTC4332

Rev. A

For more information www.analog.com

APPLICATIONS INFORMATION

baud rate supports a maximum local SCK frequency

listed in Table 2. Exceeding the listed maximum frequency

results in data loss.

The LTC4332 SPI extension solution is point-to-point

only. Multidrop or multipoint configurations on the dif-

ferential link are not allowed.

±40kV HBM ESD Protection

The LTC4332 features exceptionally robust ESD protec-

tion. The link interface pins (A, B, Y, Z) feature protection

to ±40kV HBM with respect to GND, VCC (with a 4.7μF

capacitor to GND), A, B, Y, or Z.

IEC ESD and EFT Protection

The improved ESD protection of the LTC4332 provides a

high level of protection in the IEC ESD and EFT (Electrical

Fast Transient) tests. The IEC ESD stress exceeds that of

the HBM test in peak current, amplitude, and rise time,

while the EFT test provides a prolonged repetitive stress.

Combined with the HBM test, the IEC tests help ensures

that the LTC4332 is robust under a wide range of real

world hazards. The LTC4332 passes the following tests

on the A, B, Y, Z pins:

• IEC 61000-4-2 Edition 2.0 2008-12 ESD Level 3: ±6kV

contact (A, B, Y, or Z to GND, direct discharge to bus

pins with transceiver and protection circuit mounted

on a test card with a low impedance ground discharge

path from board GND to ESD gun return lead, per

Figure 4 of the standard)

• IEC 61000-4-4 Second Edition 2004-07 EFT Level 4:

±4kV (line to GND, 5kHz repetition rate, 15ms burst

duration, 60 second test duration, discharge coupled to

bus pins through 100pF capacitor per paragraph 7.3.2

of the standard). VCC pin requires 4.7μF to meet Level

4 rating.

Startup and Shutdown

Startup occurs when supply voltages are applied to pins

VCC and VL and setting the ON pin high. All output pins are

tri-stated during the first part of startup. After an internal

initialization sequence the SPI interface and other pins

are functional. The local side LTC4332 probes the dif-

ferential link. After the startup time tREADY, a master can

access the internal control interface using the SSC slave

select pin. Once the device establishes link communica-

tion with a remote LTC4332, it drives pin LINK low and

the remote SPI bus can be accessed (TREM_READY > 0ns).

See Figure 6.

The ON pin can be used to set the LTC4332 to a lower

power state. By setting ON low, the LTC4332 is held in

reset, all programmed configuration is set to the default

value, all output drivers are disabled, and the differential

transceiver is put into low power mode. If not used, tie

ON to VL.

Link Status

The LTC4332 provides the LINK pin which indicates when

the remote SPI bus is ready. LINK is driven low when link

communication is established. It is an open-drain output

and requires an external pull-up to VL if used. At startup,

the LINK pin output driver is disabled.

Link status can also be monitored using the control inter-

face. See section Control Interface. Ensure that the values

set on local side SPEED1 and SPEED2 pins match the

values set on remote side. Also, do not the exceed the

cable length listed in Table 2. for the given SPEED setting.

The LTC4332 will not link if these conditions are not met.

Note that the link status is indeterminate if the REMOTE

pin is incorrectly configured on either the local or remote

side LTC4332 device.

Interrupt

The LTC4332 supports an interrupt signal that is mirrored

from the remote network to the local network using the

differential link when the SPI Bus is idle. On the remote

side INT is an input pin that can be connected to remote

SPI devices. While on the local side INT operates as an

open-drain output that can be connected to a shared local

interrupt line. INT is periodically sampled and has a prop-

agation time of tINT_PROP. If enabled, the local LTC4332’s

control interface uses the INT pin to report link and fault

events. The local side INT output is the logical AND of the

remote INT and the internal endpoint interrupt signal. If

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