ATF1504ASV datasheet(12/30 Pages) MICROCHIP

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 2019 Microchip Technology Inc.

DS20006185A-page 12

ATF1504ASV/ATF1504ASVL

JTAG-BST/ISP Overview

The JTAG boundary-scan testing is controlled by the

Test Access Port (TAP) controller in the ATF1504-

ASV(L). The boundary-scan technique involves the

inclusion of a shift-register stage (contained in a bound-

ary-scan cell) adjacent to each component so that sig-

nals at component boundaries can be controlled and

observed using scan testing principles. Each input pin

and I/O pin has its own boundary-scan cell (BSC) in

order to support boundary-scan testing.

The ATF1504ASV(L) does not include a Test Reset

(TRST) input pin because the TAP controller is auto-

matically reset at power-up. The five JTAG modes sup-

ported

include:

SAMPLE/PRELOAD,

EXTEST,

BYPASS, IDCODE and HIGHZ. The ATF1504ASV(L)’s

ISP can be fully described using JTAG’s BSDL as

described in IEEE Standard 1149.1. This allows

ATF1504ASV(L) programming to be described and

implemented using any one of the third-party develop-

ment tools supporting this standard.

The ATF1504ASV(L) has the option of using four

JTAG-standard I/O pins for boundary-scan testing

(BST) and in-system programming (ISP) purposes.

The ATF1504ASV(L) is programmable through the four

JTAG pins using the IEEE standard JTAG program-

ming protocol established by IEEE Standard 1149.1

using 3.3V TTL/CMOS-level programming signals from

the ISP interface for in-system programming. The

JTAG feature is a programmable option. If JTAG (BST

or ISP) is not needed, then the four JTAG control pins

are available as I/O pins.

JTAG Boundary-Scan Cell (BSC)

The ATF1504ASV(L) contains up to 64 I/O pins and

four input pins, depending on the device type and pack-

age type selected. Each input pin and I/O pin has its

own boundary-scan cell (BSC) in order to support

boundary-scan testing as described in detail by IEEE

Standard 1149.1. A typical BSC consists of three cap-

ture registers or scan registers and up to two update

registers.

There are two types of BSCs, one for input or I/O pin,

and one for the macrocells. The BSCs in the device are

chained together through the capture registers. Input to

the capture register chain is fed in from the TDI pin

while the output is directed to the TDO pin. Capture

registers are used to capture active device data sig-

nals, to shift data in and out of the device and to load

data into the update registers. Control signals are gen-

erated internally by the JTAG TAP controller. The BSC

configuration for the input and I/O pins and macrocells

are shown in Figure 1-3 and Figure 1-4.

TABLE 1-5:

POWER-DOWN AC CHARACTERISTICS(1)(2)(3)

Symbol

Parameter

-15

-20

Units

Min.

Max.

Min.

Max.

tIVDH

Valid I, I/O before PD High

—

tGVDH

Valid OE(2) before PD High

—

tCVDH

Valid Clock(2) before PD High

—

tDHIX

I, I/O Don’t Care after PD High

—

tDHGX

OE(2) Don’t Care after PD High

—

tDHCX

Clock(2) Don’t Care after PD High

—

tDLIV

PD Low to Valid I, I/O

—

µs

tDLGV

PD Low to Valid OE (Pin or Term)

—

µs

tDLCV

PD Low to Valid Clock (Pin or Term)

—

µs

tDLOV

PD Low to Valid Output

—

µs

Note 1: For slow slew outputs, add tSSO.

2: Pin or product term.

3: Includes tRPA for reduced-power bit enabled.

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