 2019 Microchip Technology Inc.

DS20006185A-page 11

ATF1504ASV/ATF1504ASVL

FIGURE 1-1:

INPUT TEST WAVEFORMS AND MEASUREMENT LEVELS

FIGURE 1-2:

OUTPUT AC TEST LOADS

Power-Down Mode

The ATF1504ASV(L) includes an optional pin-con-

trolled power-down feature. When this mode is

enabled, the PD pin acts as the power-down pin. When

the PD pin is high, the device supply current is reduced

to less than 5 mA. During power-down, all output data

and internal logic states are latched internally and held.

Therefore, all registered and combinatorial output data

remain valid. Any outputs that were in a high Z state at

the onset will remain at high Z. During power-down, all

input signals except the Power-Down pin are blocked.

Input and I/O hold latches remain active to ensure that

pins do not float to indeterminate levels, further reduc-

ing system power. The Power-Down mode feature is

enabled in the logic design file or as a design software

option. Designs using the Power-Down pin may not use

the PD pin as a logic array input. However, all other PD

pin macrocell resources may still be used, including the

buried feedback and foldback product term array

inputs.

tRPA

Reduced-Power Adder(1)

—

10

—

13

ns

Note 1: The tRPA parameter must be added to the tLAD, tLAC, tIC, tACL or tACH, tEN and tSEXP parameters for

macrocells running in the Reduced-Power mode.

TABLE 1-4:

AC CHARACTERISTICS (CONTINUED)

Symbol

Parameter

-15

-20

Units

Min.

Max.

Min.

Max.

Note:

tR, tF = 1.5 ns typical

R1 = 703

3.0V

OUTPUT

PIN

CL = 35 pF

R2 = 8060