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MFS5600AMMA7ES датащи(PDF) 49 Page - NXP Semiconductors |
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MFS5600AMMA7ES датащи(HTML) 49 Page - NXP Semiconductors |
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49 / 111 page ![]() NXP Semiconductors FS5600 Automotive buck regulator and controller with voltage monitors and watchdog timer PGOOD1_STUCK_AT_1 = 1 indicates that PGOOD1 pin is stuck at 1. PGOOD1_STUCK_AT_0 = 1 indicates that PGOOD1 pin is stuck at 0. PGOOD2_STUCK_AT_1 = 1 indicates that PGOOD2 pin is stuck at 1. PGOOD2_STUCK_AT_0 = 1 indicates that PGOOD2 pin is stuck at 0. FS0B_STUCK_AT_1 = 1 indicates that FS0B pin is stuck at 1. FS0B_STUCK_AT_0 = 1 indicates that FS0B pin is stuck at 0. During ABIST, the PGOOD1, PGOOD2, and FS0B are to be checked to ensure they are at logic low. If any of them is not at logic low during ABIST, the corresponding 'STUCK_AT_1' bit is set. When the FS56 releases PGOOD1, PGOOD2 or FS0B high, it monitors the pin to ensure it is at logic high. If not, the corresponding 'STUCK_AT_0' bit is set set. Note: There is no state transition due to stuck-at-faults. The FS5600 only reports stuck at faults via the corresponding I2C bits. System software should evaluate the status of these bits to control state transitions. 17.9 I2C robustness 17.9.1 I2C CRC verification When this feature is enabled, a selectable CRC verification is performed on each I2C transaction. When OTP_I2C_CRC_EN = 0, the CRC verification mechanism is disabled. When OTP_I2C_CRC_EN = 1, the CRC verification mechanism is enabled. After each I2C transaction, the device calculates the corresponding CRC byte to ensure the configuration command has not been corrupted. When a CRC fault is detected, the FS5600 ignores the erroneous configuration command and sets the CRC_I bit. The CRC_I is cleared by writing a 1 to it. The FS5600 implements a CRC-8-SAE, per the SAE J1850 specification. Polynomial = 0x11D Initial value = 0xFF Figure 18 shows the 8-bit CRC polynomial per SAE J1850. aaa-028696 7 MSB Data 6 5 4 1 0 3 I2C CRS Polynominal Seed: 1 1 1 1 1 1 1 1 2 Figure 18. 8-bit CRC Polynomial FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Product data sheet Rev. 3 — 2 August 2022 49 / 111 |
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