NRF9160-SIBA-R7 datasheet(31/400 Pages) NORDIC

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Application core

UICR protection bit status

NVMC protection

SECUREAPPROTECT APPROTECT

ERASEPROTECT

CTRL-AP

ERASEALL

NVMC

ERASEALL

Available

Blocked

Available

Blocked

Table 9: NVMC protection (1 - Enabled, 0 - Disabled, X - Don't care)

Note: Erase can still be performed through CTRL-AP, regardless of the above settings. See CTRL-AP

- Control access port on page 372 for more information.

Uploading code with secure debugging blocked

Non-secure code can program non-secure flash regions. In order to perform these operations, the NVMC

has the following non-secure registers: CONFIGNS, READY and READYNEXT.

transactions. Both page erase and writing inside the flash require a write transaction (see Erasing a secure

page in flash on page 30 or Erasing a non-secure page in flash on page 30). Because of this, the

SPU — System protection unit on page 259 will guarantee that the non-secure code cannot write inside

a secure page, since the transaction will never reach the NVMC controller.

4.4.6.2 NVMC power failure protection

NVMC power failure protection is possible through use of power-fail comparator that is monitoring power

supply.

If the power-fail comparator is enabled, and the power supply voltage is below VPOF threshold, the power-

fail comparator will prevent the NVMC from performing erase or write operations in non-volatile memory

(NVM).

If a power failure warning is present at the start of an NVM write or erase operation, the NVMC will block

the operation and a bus error will be signalled. If a power failure warning occurs during an ongoing NVM

write operation, the NVMC will try to finish the operation. And if the power failure warning persists,

consecutive NVM write operations will be blocked by the NVMC, and a bus error will be signalled. If a

power failure warning occurs during an NVM erase operation, the operation is aborted and a bus error is

signalled.

4.4.7 Cache

An instruction cache (I-Cache) can be enabled for the ICODE bus in the NVMC.

See Memory map on page 23 for the location of flash.

A cache hit is an instruction fetch from the cache, and it has a 0 wait-state delay. The number of wait-

states for a cache miss, where the instruction is not available in the cache and needs to be fetched from

flash, depends on the processor frequency, see CPU parameter W_FLASHCACHE.

Enabling the cache can increase the CPU performance, and reduce power consumption by reducing the

number of wait cycles and the number of flash accesses. This will depend on the cache hit rate. Cache

draws current when enabled. If the reduction in average current due to reduced flash accesses is larger

than the cache power requirement, the average current to execute the program code will be reduced.

When disabled, the cache does not draw current and its content is not retained.

4418_1315 v2.0

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