NRF9160-SIBA-R7 datasheet(83/400 Pages) NORDIC

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Peripherals

Enable CRYPTOCELL subsystem

Bit number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reset 0x00000000

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R/W

Field

Value ID

Value

Description

ENABLE

Enable or disable the CRYPTOCELL subsystem

Disabled

CRYPTOCELL subsystem disabled

Enabled

CRYPTOCELL subsystem enabled.

When enabled the CRYPTOCELL subsystem can be initialized and

controlled through the CryptoCell firmware API.

6.1.8 Host interface

This chapter describes host registers used to control the CRYPTOCELL subsystem behavior.

6.1.8.1 HOST_RGF block

The HOST_RGF block contains registers for configuring LCS and device root key KDR, in addition to selecting

which cryptographic key is connected to the AES engine.

6.1.8.1.1 Registers

Base address Peripheral

Instance

Secure mapping

DMA security

Description

Configuration

0x50840000

CC_HOST_RGF CC_HOST_RGF S

NSA

Host platform interface

Table 31: Instances

Offset

Security Description

HOST_CRYPTOKEY_SEL

0x1A38

AES hardware key select

HOST_IOT_KPRTL_LOCK

0x1A4C

This write-once register is the K_PRTL lock register. When this register is set, K_PRTL cannot

be used and a zeroed key will be used instead. The value of this register is saved in the

CRYPTOCELL AO power domain.

HOST_IOT_KDR0

0x1A50

This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO

power domain. Reading from this address returns the K_DR valid status indicating if K_DR is

successfully retained.

HOST_IOT_KDR1

0x1A54

This register holds bits 63:32 of K_DR. The value of this register is saved in the CRYPTOCELL

AO power domain.

HOST_IOT_KDR2

0x1A58

This register holds bits 95:64 of K_DR. The value of this register is saved in the CRYPTOCELL

AO power domain.

HOST_IOT_KDR3

0x1A5C

This register holds bits 127:96 of K_DR. The value of this register is saved in the CRYPTOCELL

AO power domain.

HOST_IOT_LCS

0x1A60

Controls lifecycle state (LCS) for CRYPTOCELL subsystem

Table 32: Register overview

6.1.8.1.1.1 HOST_CRYPTOKEY_SEL

Address offset: 0x1A38

AES hardware key select

Note: If the HOST_IOT_KPRTL_LOCK register is set, and the HOST_CRYPTOKEY_SEL register set to 1,

then the HW key that is connected to the AES engine is zero

4418_1315 v2.0

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