NRF9160-SIBA-R7 datasheet(30/400 Pages) NORDIC

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Application core

4.4.2 Erasing a secure page in flash

When secure region erase is enabled (in CONFIG register), a flash page can be erased by writing

0xFFFFFFFF into the first 32-bit word in a flash page.

Page erase is only applicable to the code area in the flash and does not work with UICR.

After erasing a flash page, all bits in the page are set to '1'. The time it takes to erase a page is specified by

tERASEPAGE. The CPU is stalled if the CPU executes code from the flash while the NVMC performs the erase

operation.

See Partial erase of a page in flash for information on splitting the erase time in smaller chunks.

4.4.3 Erasing a non-secure page in flash

When non-secure region erase is enabled, a non-secure flash page can be erased by writing 0xFFFFFFFF

into the first 32-bit word of the flash page.

Page erase is only applicable to the code area in the flash and does not work with UICR.

After erasing a flash page, all bits in the page are set to '1'. The time it takes to erase a page is specified by

tERASEPAGE. The CPU is stalled if the CPU executes code from the flash while the NVMC performs the erase

operation.

4.4.4 Writing to user information configuration registers (UICR)

User information configuration registers (UICR) are written in the same way as flash. After UICR has been

written, the new UICR configuration will only take effect after a reset.

UICR is only accessible by secure code. Any write from non-secure code will be faulted.

In order to lock the chip after uploading non-secure code, a simple sequence must be followed:

1. Block access to secure code by setting UICR register SECUREAPPROTECT on page 42 to protected

2. Use the WRITEUICRNS on page 35 register, via non-secure debugger, in order to set APPROTECT

(APPROTECT is automatically written to 0x00000000 by the NVMC)

UICR can only be written nWRITE number of times before an erase must be performed using ERASEALL.

The time it takes to write a word to the UICR is specified by tWRITE. The CPU is stalled if the CPU executes

code from the flash while the NVMC is writing to the UICR.

4.4.5 Erase all

When erase is enabled, the whole flash and UICR can be erased in one operation by using the ERASEALL

This functionality can be blocked by some configuration of the UICR protection bits, see the table NVMC

protection (1 - Enabled, 0 - Disabled, X - Don't care) on page 31.

The time it takes to perform an ERASEALL on page 33 command is specified by tERASEALL. The CPU is

stalled if the CPU executes code from the flash while the NVMC performs the erase operation.

4.4.6 NVMC protection mechanisms

This chapter describes the different protection mechanisms for the non-volatile memory.

4.4.6.1 NVMC blocking

UICR integrity is assured through use of multiple levels of protection. UICR protection bits can be

configured to allow or block certain operations.

The table below shows the different status of UICR protection bits, and which operations are allowed or

blocked.

4418_1315 v2.0

NRF9160-SIBA-R7 датащи(PDF) 30 Page - Nordic Semiconductor