NRF9160-SIBA-R7 datasheet(99/400 Pages) NORDIC

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Peripherals

• The GPIO pad must be low (or high depending on the SENSE polarity) for 3 CPU clock cycles after

DETECT has gone high to generate a new DETECT signal.

Note: When a pin is configured as digital input, care has been taken to minimize increased current

consumption when the input voltage is between VIL and VIH. However, it is a good practice to

ensure that the external circuitry does not drive that pin to levels between VIL and VIH for a long

period of time.

6.4.2 Pin sense mechanism

Pins sensitivity can be individually configured, through the SENSE field in the PIN_CNF[n] register, to detect

either a high level or a low level on their input.

When the correct level is detected on any such configured pin, the sense mechanism will set the DETECT

signal high. Each pin has a separate DETECT signal. Default behavior, defined by the DETECTMODE register,

is that the DETECT signals from all pins in the GPIO port are combined into one common DETECT signal

that is routed throughout the system, which then can be utilized by other peripherals. This mechanism is

functional in both System ON and System OFF modes.

DETECTMODE and DETECTMODE_SEC are provided to handle secure and non-secure pins.

DETECTMODE_SEC register is available to control the behavior associated to pin marked as secure, while

the DETECTMODE register is restricted to pin marked as non-secure. Please refer to GPIO security on page

100 for more details.

Make sure that a pin is in a level that cannot trigger the sense mechanism before enabling it. The DETECT

signal will go high immediately if the SENSE condition configured in the PIN_CNF registers is met when the

sense mechanism is enabled. This will trigger a PORT event if the DETECT signal was low before enabling

the sense mechanism.

The DETECT signal is also used by power and clock management system to exit from System OFF mode,

and by GPIOTE to generate the PORT event. In addition GPIOTE_SEC is used for PORT event related to

secure pins). See POWER — Power control on page 64 and GPIOTE — GPIO tasks and events on page

106 for more information about how the DETECT signal is used.

When a pin's PINx.DETECT signal goes high, a flag will be set in the LATCH register. For example, when

the PIN0.DETECT signal goes high, bit 0 in the LATCH register will be set to '1'. If the CPU performs a clear

operation on a bit in the LATCH register when the associated PINx.DETECT signal is high, the bit in the

LATCH register will not be cleared. The LATCH register will only be cleared if the CPU explicitly clears it by

writing a '1' to the bit that shall be cleared, i.e. the LATCH register will not be affected by a PINx.DETECT

signal being set low.

The LDETECT signal will be set high when one or more bits in the LATCH register are '1'. The LDETECT signal

will be set low when all bits in the LATCH register are successfully cleared to '0'.

If one or more bits in the LATCH register are '1' after the CPU has performed a clear operation on the

LATCH registers, a rising edge will be generated on the LDETECT signal. This is illustrated in DETECT signal

behavior on page 100.

Note: The CPU can read the LATCH register at any time to check if a SENSE condition has been met

on one or more of the the GPIO pins, even if that condition is no longer met at the time the CPU

queries the LATCH register. This mechanism will work even if the LDETECT signal is not used as the

DETECT signal.

The LDETECT signal is by default not connected to the GPIO port's DETECT signal, but via the DETECTMODE

LDETECT signal instead. See GPIO port and the GPIO pin details on page 98. DETECT signal behavior on

page 100 illustrates the DETECT signal behavior for these two alternatives.

4418_1315 v2.0

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