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SigmaTel, Inc.
Data Sheet
STAC9721
37
04/07/00
04/07/00
9.7 ATE Test Mode
Figure 19. ATE Test Mode
RESET#
SDATA_OUT
SDATA_IN, BIT_CLK
Toff
Hi-Z
Tsetup2rst
Table 29. ATE Test Mode
Parameter
Symbol
Min
Typ
Max
Units
Setup to trailing edge of RESET#
(also applies to SYNC)
ToffTsetup2rst
15.0
-
-
ns
Setup to trailing edge of RESET#
(also applies to SYNC)
Tsetup2rst
15.0
-
-
ns
Rising edge of RESET# to Hi-Z delay
Toff
-
-
25.0
ns
Notes:
1. All AC-Link signals are normally low through the trailing edge of RESET#. Bringing SDATA_OUT high for the
trailing edge of RESET# causes STAC9721/23’s AC-Link outputs to go high impedance which is suitable for
ATE in circuit testing.
2. Once either of the two test modes have been entered, the STAC9721/23 must be issued another RESET# with all
AC-Link signals low to return to the normal operating mode.
# denotes active low.
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