SigmaTel, Inc.
Data Sheet
STAC9721
16
04/07/00
04/07/00
corresponding 12 time slots are assigned to input data streams, and that they contain valid
data. The following diagram illustrates the time slot based AC-Link protocol.
Figure 7. STAC9721/23 Audio Input Frame
SYNC
BIT_CLK
SDATA_IN
valid
Frame slot1
slot2
End of previous audio frame
slot(12) "0"
"0"
"0"
19
"0"
"0"
"0"
19
19
19
"0"
Data Phase
20.8 uS (48 kHZ)
Tag Phase
12.288 MHz
Time Slot "Valid" Bits
Slot 1
Slot 2
Slot 3
Slot 12
("1" = time slot contains valid PCM data)
A new audio input frame begins with a low to high transition of SYNC. SYNC is synchronous to the rising edge of
BIT_CLK. On the immediately following falling edge of BIT_CLK, STAC9721/23 samples the assertion of SYNC.
This falling edge marks the time when both sides of AC-Link are aware of the start of a new audio frame. On the next
rising of BIT_CLK, the STAC9721/23 transitions SDATA_IN into the first bit position of slot 0 ("Codec Ready" bit).
Each new bit position is presented to AC-Link on a rising edge of BIT_CLK and subsequently sampled by the AC'97
controller on the following falling edge of BIT_CLK. This sequence ensures that data transitions, and subsequent
sample points for both incoming and outgoing data streams are time aligned.
Figure 8. Start of an Audio Input Frame
SYNC
BIT_CLK
SDATA_IN
first SDATA_OUT bit of frame here
SYNC assertion here
Codec
Ready
slot1
slot2
End of previous audio frame
SDATA_IN's composite stream is MSB justified (MSB first) with all non-valid bit positions (for assigned and/or
unassigned time slots) stuffed with 0's by STAC9721/23. SDATA_IN data is sampled on the falling edges of
BIT_CLK.
3.1.2.1
Slot 1: Status Address Port
The status port is used to monitor status for STAC9721/23 functions including, but not
limited to, mixer settings, and power management.
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