SigmaTel, Inc.
Data Sheet
STAC9721
32
04/07/00
04/07/00
6.2 Secondary Codec Register Access Definitions
The AC'97 Digital Controller can independently access Primary and Secondary Codec registers by using
a 2-bit Codec ID field (chip select) which is defined as the LSBs of Output Slot 0. For Secondary Codec
access, the AC'97 Digital Controller must invalidate the tag bits for Slot 1 and 2 Command Address and
Data (Slot 0, bits 14 and 13) and place a non-zero value (01, 10, or 11) into the Codec ID field (Slot 0,
bits 1 and 0).
As a Secondary Codec, the STAC9721/23 will disregard the Command Address and Command Data
(Slot 0, bits 14 and 13) tag bits when it sees a 2-bit Codec ID value (Slot 0, bits 1 and 0) that matches its
configuration. In a sense the Secondary Codec ID field functions as an alternative Valid Command
Address (for Secondary reads and writes) and Command Data (for Secondary writes) tag indicator.
Secondary Codecs must monitor the Frame Valid bit, and ignore the frame (regardless of the state of the
Secondary Codec ID bits) if it is not valid. AC'97 Digital Controllers should set the frame valid bit for a
frame with a secondary register access, even if no other bits in the output tag slot except the Secondary
Codec ID bits are set.
This method is designed to be backward compatible with existing AC'97 controllers and Codecs. There is
no change to output Slot 1 or 2 definitions.
Table 22. Secondary Codec Register Access Slot 0 Bit Definitions
Output Tag Slot (16-bits)
Bit
Description
15
Frame Valid
14
Slot 1 Valid Command Address bit (†Primary Codec only)
13
Slot 2 Valid Command Data bit
(†Primary Codec only)
12-3
Slot 3-12 Valid bits as defined by AC'97
2
Reserved
(Set to “0”)
†1-0
2-bit Codec ID field
(00 reserved for Primary; 01, 10, 11 indicate Secondary)
† New definitions for Secondary Codec Register Access
7. TESTABILITY
The STAC9721/23 has two test modes. One is for ATE in-circuit test and the other is restricted for
SigmaTel’s internal use. STAC9721/23 enters the ATE in circuit test mode if SDATA_OUT is sampled
high at the trailing edge of RESET#.
Once in the ATE test mode, the digital AC-Link outputs
(BIT_CLK and SDATA_IN) are driven to a high impedance state. This allows ATE in-circuit testing of
the AC'97 controller. This case will never occur during standard operating conditions. Once either of the
two test modes have been entered, the STAC9704/7 must be issued another rest with all AC-link signals
held low to return to the normal operating mode.
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