SigmaTel, Inc.
Data Sheet
STAC9721
10
04/07/00
04/07/00
2. AC-LINK
Below is the figure of the AC-Link point to point serial interconnect between the STAC9721/23 and its
companion controller. All digital audio streams and command/status information are communicated over
this AC-Link. Please refer to the “Digital Interface” section 3 for details.
Figure 3. STAC9721/23’s AC-Link to its companion controller
SYNC
BIT CLK
SDATA_OUT
SDATA_IN
RESET
Digital
DC’97
Controller
SigmaTel
AC’97 Codec
XTAL_IN
XTAL_OUT
2.1 Clocking
STAC9721/23 derives its clock internally from an externally connected 24.576 MHz crystal or an
oscillator through the XTAL_IN pin. Synchronization with the AC'97 controller is achieved through the
BIT_CLK pin at 12.288 MHz (half of crystal frequency).
The beginning of all audio sample packets, or “Audio Frames”, transferred over AC-Link is synchronized
to the rising edge of the “SYNC” signal driven by the AC'97 controller. Data is transitioned on AC-Link
on every rising edge of BIT_CLK, and subsequently sampled by the receiving side on each immediately
following falling edge of BIT_CLK.
2.2 Reset
There are 3 types of resets as detailed under “Timing Characteristics”.
• “cold” reset where all STAC9721/23 logic and registers are initialized to their default state
• “warm” reset where the contents of the STAC9721/23 register set are left unaltered
• “register” reset which only initializes the STAC9721/23 registers to their default states
After signaling a reset to the STAC9721/23, the AC'97 controller should not attempt to play or capture
audio data until it has sampled a “Codec Ready” indication via register 26h from the STAC9721/23. For
proper reset operation SDATA_OUT should be “0” during “cold” reset. See “Testability” section for
more information.
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