FDMS3604S

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12

Recommended PCB Layout Guidelines

As a PCB designer, it is necessary to address critical issues

in layout to minimize losses and optimize the performance

of the power train. Power Stage is a high power density

solution and all high current flow paths, such as VIN (D1),

PHASE (S1/D2) and GND (S2), should be short and wide

for better and stable current flow, heat radiation and system

performance. A recommended layout procedure is

discussed below to maximize the electrical and thermal

performance of the part.

Figure 31. Recommended PCB Layout

Following is a guideline, not a requirement which the PCB designer should consider:

1. Input ceramic bypass capacitors C1 and C2 must

be placed close to the D1 and S2 pins of Power

Stage to help reduce parasitic inductance and High

Frequency conduction loss induced by switching

operation. C1 and C2 show the bypass capacitors

placed close to the part between D1 and S2. Input

capacitors should be connected in parallel close to

the part. Multiple input caps can be connected

depending upon the application

2. The PHASE copper trace serves two purposes; In

addition to being the current path from the Power

Stage package to the output inductor (L), it also

serves as heat sink for the lower FET in the Power

Stage package. The trace should be short and wide

enough to present a low resistance path for the

high current flow between the Power Stage and the

inductor. This is done to minimize conduction

losses and limit temperature rise. Please note that

the PHASE node is a high voltage and high

frequency switching node with high noise

potential. Care should be taken to minimize

coupling to adjacent traces. The reference layout

in Figure 31 shows a good balance between the

thermal and electrical performance of Power Stage

3. Output inductor location should be as close as

possible to the Power Stage device for lower

power loss due to copper trace resistance. A

shorter and wider PHASE trace to the inductor

reduces the conduction loss. Preferably the Power

Stage should be directly in line (as shown in

Figure 32) with the inductor for space savings and

compactness

4. The POWERTRENCH Technology MOSFETs

used in the Power Stage are effective at

minimizing phase node ringing. It allows the part

to operate well within the breakdown voltage

limits. This eliminates the need to have an external

snubber circuit in most cases. If the designer

chooses to use an RC snubber, it should be placed

close to the part between the PHASE pad and S2

pins to dampen the high−frequency ringing

5. The driver IC should be placed close to the Power

Stage part with the shortest possible paths for the

High Side gate and Low Side gates through a wide

trace connection. This eliminates the effect of

parasitic inductance and resistance between the

driver and the MOSFET and turns the devices on

and off as efficiently as possible. At