PM8805 datasheet(27/48 Pages) STMICROELECTRONICS

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DS12813 Rev 2

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PM8805

PM8805 overview

Equation 2

The charging time may be estimated with the formula:

Equation 3

As an example, assuming a 33 uF output capacitor and 54 V input voltage, the Inrush time is

around 24.5 ms.

When the voltage across the hot swap MOSFET is completely closed (VOB-0.5 V) and its

gate voltage is higher than 5 V above VOB, all the electrical conditions are set in order to

assert the PGD signal (PGD = Hi-Z, open drain, active high) which may serve to enable an

external DC/DC converter.

Actually, when powered by PoE a PGD_Delay timer (85 ms typ.) is activated between UVLO

and PGD assertion, to ensure the PSE inrush phase is completed before increasing the PD

current consumption, as required by the IEEE802.3 standard.

This is just a minimum time, valid if the charge of the output capacitor is faster than

PGD_Delay.

It can be calculated indeed that a 110 uF capacitor takes about 84 ms to charge to 54 V; this

means that 100 uF is the maximum commercial value for the output capacitance, that

causes a standard delay time for PGD assertion. Larger capacitors would need more time to

charge, further delaying the PGD, and the consequent DC/DC startup.

The inrush phase may be initiated also when the FAUX pin is asserted: in that case, the

control logic asserts the PGD signal as soon as the hot swap MOSFET is closed, without

waiting for PGD_delay. See Section 4.11 for more details on using FAUX.

The PGD signal is the only signal exchanged with the load (e.g. DC/DC converter or LED

driver) supplied with the voltage coming from the PM8805.

PGD is an open drain signal, 100 V rated, active high; it can be pulled up to the VOUT

voltage, but must be verified if the load circuitry can accept such voltage at its input: in some

cases a Zener diode is required to clamp the max. voltage at the converter side.

Alternatively, PGD can be pulled up to a voltage coming from the load, for example the

internal start-up voltage of the DC/DC converter, typically in the range of 8-12 V.

The UVLO threshold is provided with an internal delay (100 uS typ.) that as a secondary

effect reduces the value of the protection tripping depending on the applied load; the

threshold is lower for higher power PDs.

A high value output capacitor allows to mitigate this effect: for instance, assuming a load of

71 W with the minimum UVLO specified at 30 V, using a 47 uF output capacitor the 100 us

delay introduces an additional drop of about 5 V (71 W/30 V x 100 us /47 uF) and the real

UVLO threshold is 25 V.

Iinrush = (25mA-Iload_inrush) + 3500[mA·V] / VOB

Tinrush - Cout VOB

Inrush

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