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NAND01G-B2C датащи(PDF) 32 Page - Numonyx B.V

номер детали NAND01G-B2C
подробное описание детали  1-Gbit, 2112-byte/1056-word page, 1.8 V/3 V, single level cell NAND flash memory
PDF  67 Pages
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производитель  NUMONYX [Numonyx B.V]
домашняя страница  http://www.numonyx.com
Logo NUMONYX - Numonyx B.V

NAND01G-B2C датащи(HTML) 32 Page - Numonyx B.V

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Device operations
NAND01G-B2C
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6.7.3
P/E/R controller bit (SR5)
The program/erase/read controller bit indicates whether the P/E/R controller is active or
inactive. When the P/E/R controller bit is set to ‘0’, the P/E/R controller is active (device is
busy); when the bit is set to ‘1’, the P/E/R controller is inactive (device is ready).
6.7.4
Error bit (SR0)
The error bit is used to identify if any errors have been detected by the P/E/R controller. The
error bit is set to ’1’ when a program or erase operation has failed to write the correct data to
the memory. If the error bit is set to ‘0’ the operation has completed successfully.
6.7.5
SR4, SR3, SR2, and SR1 are reserved
Table 11.
Status register bits
Bit
Name
Logic level
Definition
SR7
Write protection
'1'
Not protected
'0'
Protected
SR6
Program/ erase/ read
controller
'1'
P/E/R C inactive, device ready
'0'
P/E/R C active, device busy
Cache ready/busy
'1'
Cache register ready (cache operation only)
'0'
Cache register busy (cache operation only)
SR5
Program/ erase/ read
controller
'1'
P/E/R C inactive, device ready
'0'
P/E/R C active, device busy
SR4, SR3,
SR2, SR1
Reserved
Don’t care
SR0
Generic error
‘1’
Error – operation failed
‘0’
No error – operation successful



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