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DAC82002 датащи(PDF) 12 Page - Texas Instruments

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номер детали DAC82002
подробное описание детали  DAC82002 16-Bit, Low-Glitch-Energy, Dual-Channel Voltage-Output, Unbuffered DAC
PDF  22 Pages
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
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DAC82002 датащи(HTML) 12 Page - Texas Instruments

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7.6.1.2 SYNC Register (offset = 2h) [reset = 0300h]
Figure 7-5. SYNC Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESERVED
DAC-B-
BRDCAST-
EN
DAC-A-
BRDCAST-
EN
RESERVED
DAC-B-
SYNC-EN
DAC-A-
SYNC-EN
W-0h
W-1h
W-1h
W-0h
W-0h
W-0h
Table 7-4. SYNC Register Field Descriptions
Bit
Field
Type
Reset
Description
15-10
RESERVED
W
0h
These bits are reserved.
9
DAC-B-BRDCAST-EN
W
1h
When set to 1, the corresponding DAC is set to update the
output after a serial interface write to the BRDCAST register.
When cleared to 0, the corresponding DAC output remains
unaffected after a serial interface write to the BRDCAST
register.
8
DAC-A-BRDCAST-EN
W
1h
When set to 1, the corresponding DAC is set to update the
output after a serial interface write to the BRDCAST register.
When cleared to 0, the corresponding DAC output remains
unaffected after a serial interface write to the BRDCAST
register.
7-2
RESERVED
W
0h
These bits are reserved.
1
DAC-B-SYNC-EN
W
0h
When set to 1, the DAC output is set to update in response to an
LDAC trigger (synchronous mode).
When cleared to 0, the DAC output is set to update immediately
(asynchronous mode), default.
0
DAC-A-SYNC-EN
W
0h
When set to 1, the DAC output is set to update in response to an
LDAC trigger (synchronous mode).
When cleared to 0 ,the DAC output is set to update immediately
(asynchronous mode), default.
7.6.1.3 TRIGGER Register (offset = 5h) [reset = 0000h]
Figure 7-6. TRIGGER Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESERVED
LDAC
SOFT-RESET [3:0]
W-0h
W-0h
W-0h
Table 7-5. TRIGGER Register Field Descriptions
Bit
Field
Type
Reset
Description
15-5
RESERVED
W
0h
These bits are reserved.
4
LDAC
W
0h
Set this bit to 1 to synchronously load the DACs that are set to
synchronous mode in the SYNC register. This bit self-resets.
3-0
SOFT-RESET [3:0]
W
0h
When set to reserved code 1010, this bit resets the device to the
default state. This bit self-resets.
DAC82002
SBASAK1 – AUGUST 2022
www.ti.com
12
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Product Folder Links: DAC82002



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