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DAC82002 датащи(PDF) 9 Page - Texas Instruments

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номер детали DAC82002
подробное описание детали  DAC82002 16-Bit, Low-Glitch-Energy, Dual-Channel Voltage-Output, Unbuffered DAC
PDF  22 Pages
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
Logo TI - Texas Instruments

DAC82002 датащи(HTML) 9 Page - Texas Instruments

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7.3.2 Power-On Reset (POR)
The DAC82002 device includes a power-on reset function that controls the output voltage at power up. After the
VDD supply has been established, a POR event is issued. The POR causes all registers to initialize to default
values, and communication with the device is valid only after a 250-µs, power-on-reset delay. The default value
for all DACs is zero code if RSTSEL = AGND, and midscale code if RSTSEL = VDD. Each DAC channel remains
at the power-up voltage until a valid command is written to a channel.
When the device powers up, a POR circuit sets the device to the default mode. Figure 7-2 shows that the POR
circuit requires specific VDD levels to make sure that the internal capacitors discharge and reset the device on
power up. To make sure that a POR occurs, VDD must be less than 0.7 V for at least 1 ms. When VDD drops
to less than 2.2 V but remains greater than 0.7 V (shown as the undefined region in the image), the device may
or may not reset under all specified temperature and power-supply conditions; in this case, initiate a POR. When
VDD remains greater than 2.2 V, a POR does not occur.
No power-on reset
Power-on reset
0.70
Undefined
0.00
2.20
2.70
5.50
VDD (V)
Spe cified supply
voltage range
Figure 7-2. Threshold Levels for the VDD POR Circuit
7.3.3 Hardware Reset
The DAC output is asynchronously set to zero code if RSTSEL = AGND, and midscale code if RSTSEL = VDD,
immediately after the RESET pin is brought low. The RESET signal resets all internal registers, meaning all
registers initialize to default values. Bring the RESET pin back to high before a write sequence starts. Similar
to the POR delay, communication with the device is valid only after a 250
‑µs delay. The default value for each
DAC channel remains at the reset voltage until a valid command is written to a channel. The RSTSEL pin can
be reconfigured without a power cycle. The DAC output always reflects the current RSTSEL status when the
RESET pin is pulled low.
7.3.4 Software Reset
A device software reset event is initiated by writing the reserved code 0x1010 to the SOFT-RESET bit in the
TRIGGER register (address 5h). A software reset initiates a POR event.
7.4 Device Functional Modes
The DAC82002 has one mode of operation: normal.
In normal mode, the DAC82002 is fully operational. The device translates digital input or reset input to
corresponding analog output.
www.ti.com
DAC82002
SBASAK1 – AUGUST 2022
Copyright © 2022 Texas Instruments Incorporated
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