7.3 Feature Description

7.3.1 Digital-to-Analog Converter (DAC) Architecture

Each output channel in the DAC82002 device consists of a segmented R-2R architecture. Figure 7-1 shows

a block diagram of the DAC architecture. The four MSBs of the 16-bit data word are decoded to drive 15

switches, E1 to E15. Each of these switches connects one of 15 matched resistors to either AGND or VREF. The

remaining 12 bits of the data word drive switches S0 to S11 of a 12-bit voltage mode R-2R ladder network.

R

R

2R

GND

2R

2R

2R

2R

2R

2R

S0

12-Bit R-2R Ladder

4 MSBs Decoded into

15 Equal Segments

S1

S11

E1

E2

E15

Figure 7-1. DAC82002 DAC Block Diagram

7.3.1.1 DAC Transfer Function

The input data writes to the individual DAC data registers in straight binary format. After a power-on or a reset

transfer function is shown by Equation 1.

(1)

where:

• N = 16 (resolution in bits)

• DAC_DATA = decimal equivalent of the binary code that is loaded to the DAC register (address 8h),

7.3.1.2 DAC Register Structure

Data written to the DAC data registers are initially stored in the DAC buffer registers. The update mode of the

DAC output is determined by the status of the DAC_SYNC_EN bit (address 2h).

In asynchronous mode (default, DAC_SYNC_EN = 0), a write to the DAC buffer register results in an immediate

update of the DAC active register. The DAC output (VOUTx pin) updates on the rising edge of SYNC.

In synchronous mode (DAC_SYNC_EN = 1), writing to the DAC buffer register does not automatically update

the DAC active register. Instead, the update occurs only after a software LDAC trigger event. A software LDAC

trigger generates through the LDAC bit in the TRIGGER register (address 5h). When the host reads from a

DAC buffer register, the value held in the DAC buffer register is returned (not the value held in the DAC active

register).

DAC82002

SBASAK1 – AUGUST 2022

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