AMT49106 datasheet(21/74 Pages) ALLEGRO

21 / 74 page

Automotive Three-Phase MOSFET Driver

AMT49106

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

FUNCTIONAL DESCRIPTION

The AMT49106 provides six high current gate drives capable of

driving a wide range of N-channel power MOSFETs. The gate

drives are configured as three half bridges, each with a high-side

drive and a low-side drive. The three half bridges can be oper-

ated independently or together as a three-phase bridge driver for

BLDC or PMSM motors.

Gate drives have programmable drive strength and can be

controlled individually with logic inputs or through the

SPI-compatible serial interface. Independent control over each

MOSFET allows each driver to be driven with an independent

PWM signal for full sinusoidal excitation.

The AMT49106 requires two power supplies: an analog supply

of 4.5 to 50 V connected to VBB and a 3 to 5.5 V logic supply

connected to VIO.

The analog supply powers two internal charge pumps. The first

charge pump generates a regulated supply (VREG) to provide all

the current necessary to drive the low-side gate drive outputs plus

most of the charge necessary to drive the high-side gate drives

via the bootstrap capacitors. The second charge pump generates

an above-battery regulated supply (VCP) to ensure the bootstrap

capacitors remain adequately charged during high duty cycle

operation. This architecture ensures that all external MOSFETs

are fully enhanced at unregulated supply voltages down to 4.5 V

and PWM duty cycles over the full range of 0 to 100% without

exceptions.

The logic supply directly powers all logic input/output circuitry

(VIO) and is linearly regulated to also power the device core logic

(VDD).

All logic inputs and outputs have standard CMOS threshold

levels derived from the applied VIO. All gate drive control logic

inputs are battery voltage compliant, meaning they can be shorted

to ground or supply without damage, up to the maximum battery

voltage of 50 V.

The AMT49106 will not reset any internal states and the SPI

interface will remain active at VIO voltages down to the VIO

POR voltage (falling) threshold, VPOROFF. If VIO drops below

VIO POR voltage (falling) threshold, VPOROFF, the part may

reset—all internal states will be lost, the SPI interface will cease

to operate, and all gate drive outputs will be disabled. If the

applied VIO remains above VIO POR voltage (falling) threshold,

VPOROFF, and the VBB voltage drops below 4.5 V, it is possible

that the gate drive outputs may fall below a safe level and be

disabled. However, the device logic and SPI interface will remain

functional.

A low power sleep mode allows the AMT49106, the power

bridge, and the load to remain connected to a vehicle battery sup-

ply without the need for an additional supply switch.

The AMT49106 includes many diagnostic features to provide

indication of and/or protection against undervoltage, overvoltage,

overtemperature, and power bridge faults. Detailed diagnostic

information is available through the serial interface.

For systems requiring a higher level of safety integrity, the

AMT49106 includes additional overvoltage monitors on the sup-

plies and the control inputs. In addition, the integrated diagnos-

tics include self-test and verification circuits to ensure verifiable

diagnostic operation. When used in conjunction with appropri-

ate system level control, these features can assist power drive

systems using the AMT49106 to meet stringent ASIL D safety

requirements.

The serial interface also provides access to programmable dead

time, fault blanking time, programmable VDS threshold for short

detection, and programmable thresholds and currents for open-

load detection.

The AMT49106 includes three amplifiers designed for low-side

current sensing in the presence of high current and voltage tran-

sients. These can be used independently to provide three current

sense readouts or in combination to provide redundant sensing of

a single current. All sense amplifier signal input pins are moni-

tored to ensure they remain connected to the external current

sense resistor(s). The gain of each amplifier can be set indepen-

dently and a common pedestal (offset reference voltage) can be

applied to the OOR input pin to allow sensing of bidirectional

sense resistor current flow.

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