AMT49106 datasheet(39/74 Pages) ALLEGRO

39 / 74 page

Automotive Three-Phase MOSFET Driver

AMT49106

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

action then required to clear the fault state depend upon the

FDSO bit value.

If FDSO = 0, the fault state will be latched, the general fault flag

will be active, the associated VDS fault bit will be set and the

gate drive for the associated MOSFET will be inactive (low). The

gate drive output will remain inactive (low) until the fault state

and the general fault flag are reset the next time the MOSFET,

on which the fault was detected, is commanded to switch on. The

associated VDS fault bit remains set in the Diagnostic 1 register

until reset. If the MOSFET is being driven with a PWM signal

then this will usually mean that the MOSFET will be turned on

again each PWM cycle. If this is the case, and the fault condition

remains, then a valid fault will again be detected after the timeout

period and the sequence will repeat. The general fault flag will

only be reset for the duration of the validation timer. The VDS

fault bits will only be reset by a serial read of the Diagnostic 1

If FDSO = 1, the fault will be latched, the general fault flag will

be active, the associated VDS fault bit will be set and all gate

drive outputs will be inactive (low). The gate drive outputs will

remain inactive (low) until the fault state and the general fault

flag are reset by a serial read of the Diagnostic 1 register with

DSR = 0, or by a power-on reset. The VDS fault bit will only be

reset by a serial read of the Diagnostic 1 register with DSR = 0 or

by a power-on reset.

If FDSO = 0, care must be taken to avoid damage to the MOS-

FET where the VDS fault is detected. Although the MOSFET

will be switched off as soon as the fault is detected at the end

of the fault validation timeout, it is possible that it could still be

damaged by excessive power dissipation and heating. To limit

any damage to the external MOSFETs or the motor, the gate drive

outputs should be fully disabled by logic inputs from the external

controller.

Fault Action

The action taken when one of the diagnostic functions indicates a

fault is listed in Table 6.

When a fault is detected, a corresponding fault state is consid-

ered to exist. In some cases, the fault state only exists during the

time the fault is detected. In other cases, when the fault is only

detected for a short time, the fault state is latched (held in the

fault state) until reset. The faults that are latched are indicated

in Table 6. Latched fault states are always reset when a power-

on-reset state is present or when the associated fault bit is read

through the serial interface with DSR = 0. Any fault bits that have

been set in the diagnostic registers are only reset when a power-

on-reset state is present or when the associated fault bit is read

through the serial interface with DSR = 0.

For most of the diagnostic functions, the action taken when a

fault state is detected can be programmed to force the gate drive

outputs into the inactive (low) state or to leave them active. The

action is selected by setting a 1 or 0 in specific stop on fault

(SoF) bit associated with the diagnostic. The specific SoF bits for

each diagnostic and the actions taken for each setting are listed in

Table 6.

Table 6: Fault Actions

Fault Description

SoF Bit

Name

Disable Outputs

Fault State

Latched

SoF

Bit = 0

SoF

Bit = 1

No Fault

–

Power-on-Reset

–

Yes [1]

VREG Undervoltage

FVRU

No [3]

Yes [1]

VCP Undervoltage

FCPU

Yes

VIO or VOOR Out of Range

FVDD

Yes [1]

Bootstrap Undervoltage

FVBU

Yes [1]

Logic Terminal Overvoltage

FVLO

Yes [1][4]

WD Timeout

FWD

Yes [1]

Yes

Overtemperature

FOT

No [3]

Yes [1]

LSS Disconnect

FLSS

Yes [5]

Yes

VDS Fault

FDSO

Yes [2]

Yes [1]

Yes

Serial Transmission Error

FSE

Yes [1]

VREG Overvoltage

FVRO

Yes [1]

VBB Undervoltage

FVSU

No [3]

Yes [1]

VBB Overvoltage

FVSO

Yes [1]

VGS Undervoltage

FGSU

No [3]

Yes [1]

Yes

Temperature Warning

FTW

Yes [1]

Overcurrent

FOC

Yes [1]

Yes

Open Load

–

EEPROM

–

Yes [1]

Yes

[1]

All gate drives low, all MOSFETs off.

[2]

Gate drive for the affected MOSFET low, only the affected MOSFET off.

[3]

Stated fault condition may damage the AMT49106 and/or bridge MOSFETs

unless appropriate action taken by the external controller.

[4]

Outputs disabled on Hx, Lx, overvoltage but not on DIAG, ENABLE overvoltage.

[5]

Creates VDS fault.

If a Power-on-Reset state is detected, then all gate drive outputs

are driven low and all MOSFETs in the bridge are held in the off-

state. This persists until the Power-on-Reset state is cleared.

Setting any of the FVRU, FCPU, FVDD, FVBU, FVLO, FWD,

FDSO, FSE, FVRO, FVSU, FVSO, FOT, FTW, FOC, FLSS, or

FGSU bits in the Stop-on-Fault registers to 0 such that the gate

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