LT8350RVPBF datasheet(19/24 Pages) AD

19 / 24 page

LT8350

Rev. 0

For more information www.analog.com

Programming VIN UVLO

A resistor divider from VIN to the EN/UVLO pin imple-

ments VIN undervoltage lockout (UVLO). The EN/UVLO

enable falling threshold is set at 1.220V with 15mV hyster-

esis. In addition, the EN/UVLO pin sinks 2.5µA when the

voltage on the pin is below 1.220V. This current provides

user programmable hysteresis based on the value of R1.

The programmable UVLO thresholds are:

VIN(UVLO+) = 1.235V •

+ 2.5µA • R1

R1 + R2

VIN(UVLO–) = 1.220V •

R1 + R2

Figure 12 shows the implementation of external shutdown

control while still using the UVLO function. The NMOS

grounds the EN/UVLO pin when turned on, and puts the

LT8350 in shutdown with quiescent current less than

2µA (typical).

VIN

RUN/STOP

CONTROL

(OPTIONAL)

8350 F12

EN/UVLO

GND

LT8350

Figure 12. VIN Undervoltage Lockout (UVLO)

Programming Input or Output Current Limit

The input or output current limit is programmed by plac-

ing an appropriate value current sense resistor, RIS, in

the input or output power path. The voltage drop across

RIS is (Kelvin) sensed by the ISP and ISN pins. The CTRL

pin should be tied to a voltage higher than 1.35V to get

the full-scale 100mV (typical) threshold across the sense

resistor. The CTRL pin can be used to reduce the input

or output current to zero, although relative accuracy

decreases with the decreasing sense threshold. When

the CTRL pin voltage, VCTRL, is less than 1.15V, the cur-

rent limit is:

IIS(MAX) =

VCTRL – 0.25V

10 • RIS

When VCTRL is higher than 1.35V, the current threshold

is regulated to:

IIS(MAX) =

100mV

RIS

The CTRL pin should not be left open (tie to VREF if not

used). The CTRL pin can also be used in conjunction with

a thermistor to provide overtemperature protection for

the output load, or with a resistor divider to VIN to reduce

output power and switching current when VIN is low.

The presence of a time varying differential voltage ripple

signal across ISP and ISN at the switching frequency is

expected. The amplitude of this signal is increased by

higher load current, lower switching frequency, or smaller

value output filter capacitor. Some level of ripple signal

is acceptable, and the compensation capacitor on the VC

pin filters the signal so the average difference between

ISP and ISN is regulated to the user-programmed value.

The ripple voltage amplitude (peak-to-peak) in excess of

20mV should not cause mis-operation, but may lead to

noticeable offset between the average value and the user-

programmed value.

ISMON Current Monitor

The ISMON pin provides a buffered monitor output of the

current flowing through the ISP/ISN current sense resis-

tor, RIS. The ISMON voltage is calculated as:

VISMON = 10 • V(ISP – ISN) + 250mV

Since the ISMON pin has the same 0.25V offset as the

CTRL pin, the primary LT8350 ISMON pin can be directly

tied to the secondary LT8350 pin for equal current sharing

in parallel applications.

LOAD Switch Control

The LOADEN and LOADTG pins provide high side PMOS

load switch control. The LOADEN pin accepts a logic level

ON/OFF signal and then drives the LOADTG pin to turn on

or off the high side PMOS load switch, thereby connect-

ing or disconnecting the LT8350 power output from the

system output. When the LOADEN pin is force low, the

LT8350 turns off power switches, disconnects the VC pin

APPLICATIONS INFORMATION

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